以太网数传系统在FPGA上的实现

发布时间：2018-05-12 20:07

  本文选题：嵌入式以太网 + 数据传输　； 参考：《液晶与显示》2017年08期

【摘要】：在含有FPGA的数字信号处理电路和控制电路中,为了实现将原始AD采样数据或中间处理结果数据的导出,供后续分析处理使用,从数据传输的稳定性、系统实现的简易性、价格低廉等角度出发,研究设计了基于FPGA TSE IP核的嵌入式百兆以太网数据传输系统。首先,详细分析了以NiosII CPU软核处理器为核心的以太网数传系统的SOPC各模块的硬件设计,主要包括以TES IP核为主的以太网MAC,采用乒乓缓存方式保证数据的连续不间断传输,以及通过接收客户端指令来控制数传的开始和暂停;然后,利用MicroC/OS-II嵌入式实时操作系统的多任务方式,基于Niche stack TCP/IP协议栈,完成了系统的软件设计,并给出了软件程序流程;最后,通过传输并接收特定的数据,验证了系统数据传输的速率和准确性。结果表明在传输速率达到51 Mbps时,系统稳定可靠。
[Abstract]:In the digital signal processing circuit and control circuit containing FPGA, in order to export the original AD sampling data or intermediate processing result data for subsequent analysis and processing, the stability of data transmission and the simplicity of system realization are obtained. From the point of view of low price, the embedded data transmission system based on FPGA TSE IP core is studied and designed. Firstly, the hardware design of SOPC module of Ethernet data transmission system based on NiosII CPU soft core processor is analyzed in detail, which mainly includes Ethernet Mac, which is based on TES IP core, and uses ping-pong buffer to ensure the continuous transmission of data. Then, using the multi-task mode of MicroC/OS-II embedded real-time operating system, based on the Niche stack TCP/IP protocol stack, the software design of the system is completed, and the software program flow is given. Finally, the rate and accuracy of system data transmission are verified by transmitting and receiving specific data. The results show that the system is stable and reliable when the transmission rate reaches 51 Mbps.
【作者单位】： 中国科学院长春光学精密机械与物理研究所;电子科技大学通信与信息工程学院;
【分类号】：TN791;TP393.11
，

本文编号：1879977