基于FPGA的嵌入式以太网接口设计

发布时间：2018-05-17 14:43

本文选题：数据采集 + 网络协议　；参考：《西安电子科技大学》2014年硕士论文

【摘要】：计算机和通信技术的迅猛发展,刺激着各个领域的进步,特别是航空领域。少量的信息采集、记录和显示已经无法满足机载数据采集系统的需求,正往大量实时信号的记录、处理、存储和传输方向发展。在机载采集系统上安装着大量的传感器,这些传感器能采集飞机飞行过程的环境信息,包括飞行高度、气流压力、温度、风向等。这些飞行环境经过传感器输出为数字电平,电平经过采样、量化、编码等步骤,以码元的形式通过以太网实时传输送入计算机进行处理、分析、存储和显示。作为数据采集系统的核心,微处理器一般都提供以太网接口,当大量采集数据到来时,其处理任务和网络传输之间的矛盾就越发突出。在本文,大量模拟信号的实时传输,需要处理器的不断运转,考虑到减少处理器的运算压力、对采集系统FPGA资源的合理使用和飞行环境对机载设备体积、功耗等方面提出的严格要求,以嵌入式以太网为基础,提出了基于FPGA的嵌入式以太网接口设计的方案。论文主要工作如下:1、本文基于FPGA的高性价比、应用广泛和可灵活编程的特点,采用了软硬件协同编程的方式完成设计。以Altera公司的CycloneIII系列为平台,搭建了以软核处理器NiosII为核心包含多种外设的可编程片上系统(SoPC),其中最主要的外设是以太网的核心媒体接入控制器(MAC)。利用Altera公司的三速以太网(TSE)IP核,在FPGA内实现以太网MAC协议,并提供了标准介质独立接口(MII)。该接口与扩展的物理(PHY)芯片相连,完成网络传输的底层设计。PHY芯片DP83640,该芯片体积小、功耗低但功能强大,并提供了精简介质独立接口(RMII)。2、网络接口设计位于网络通信的最底层,为了实现完整的以太网通信,在软件设计中,完成了三速以太网MAC和DP83640的驱动设计,并系统的移植了轻量级TCP/IP协议栈——Lwip,为了减少内存占用,本文是移植无操作系统Lwip,并根据协议栈实现了UDP的数据传输,并提供了上层应用程序调用的接口(API)。基于FPGA的嵌入式以太网接口设计从机载数据采集环境需求出发,充分利用了FPGA的高速、实时、可编程特性,经过测试,网络传输性能达到了系统指标要求。
[Abstract]:The rapid development of computer and communication technology stimulates the progress in various fields, especially in aviation. A small amount of information acquisition, recording and display can no longer meet the requirements of airborne data acquisition system, and is developing towards the direction of recording, processing, storage and transmission of a large number of real-time signals. A large number of sensors are installed on the airborne acquisition system, which can collect the environmental information of the flight process of the aircraft, including flight altitude, air pressure, temperature, wind direction and so on. These flying environments are output to digital level by sensor, the level is sampled, quantized, coded and sent to computer to process, analyze, store and display through Ethernet real-time transmission in the form of symbol. As the core of data acquisition system, microprocessor generally provides Ethernet interface. When a large amount of data is collected, the contradiction between processing task and network transmission becomes more and more prominent. In this paper, the real-time transmission of a large number of analog signals requires the continuous operation of the processor. In order to reduce the computational pressure of the processor, the reasonable use of the FPGA resources of the acquisition system and the volume of the airborne equipment in the flight environment are considered. Based on the strict requirement of power consumption and embedded Ethernet, the design of embedded Ethernet interface based on FPGA is proposed. The main work of this paper is as follows: 1. Based on the high performance-to-price ratio of FPGA, this paper has the characteristics of wide application and flexible programming, and adopts the method of hardware and software co-programming to complete the design. Based on the CycloneIII series of Altera Company, a programmable on-chip system with a soft core processor NiosII as the core is built, in which the main peripheral device is the Ethernet core media access controller (MAC). Using Altera's three-speed Ethernet TSE IP core, the Ethernet MAC protocol is implemented in FPGA, and a standard medium independent interface is provided. The interface is connected with the extended PHY chip, and the bottom design of the network transmission is DP83640. The chip is small, low power and powerful, and provides the RMII / 2 independent interface. The network interface design lies at the bottom of the network communication. In order to realize the complete Ethernet communication, the driver design of three-speed Ethernet MAC and DP83640 is completed in the software design, and the lightweight TCP/IP protocol stack is transplanted into the system. In this paper, we transplant the Lwip without operating system, realize the data transmission of UDP according to the protocol stack, and provide the interface of calling by the upper application program. The design of embedded Ethernet interface based on FPGA is based on the requirement of airborne data acquisition environment, and makes full use of the high-speed, real-time and programmable characteristics of FPGA. After testing, the network transmission performance meets the requirements of the system.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP393.11

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