IP路由器片上系统的设计与性能仿真

发布时间：2018-07-03 09:23

本文选题：IP路由器 + 片上系统　；参考：《系统仿真学报》2013年12期

【摘要】：为了应对IP(Internet Protocol)路由器在性能、扩展性方面的挑战,提出并设计了一种基于大规模并行处理片上系统(MPPSoC,Massively Parallel Processing System on Chip)体系结构的IP路由器片上系统,该片上系统结构中使用大量的、同构的处理单元进行IP分组处理,并通过扩展性良好的SD-Torus(Semi-Diagonal Torus)片上网络(NoC,Network on Chip)进行片内互连,实现了分布式的转发和交换。重点研究了IP路由器片上系统中同构处理单元的结构、片内互连网络拓扑结构的选择、地址查找和分组交换功能在各个处理单元上的映射等关键问题。使用硬件描述语言SystemC,对该IP路由器片上系统进行了建模,并通过采用不同的IP分组流量模型,在不同的网络规模、不同负载程度下,对路由器片上系统的性能,包括系统吞吐量、平均延迟以及延迟抖动等关键性能参数进行了仿真。仿真结果表明,该结构具有良好的系统性能和扩展性。
[Abstract]:In order to meet the performance and scalability challenges of IP (Internet Protocol) routers, this paper proposes and designs an on-chip system for IP routers based on the MPPSoC Massively parallel processing system on Chip architecture. The isomorphic processing unit is processed by IP packet processing and interconnects on chip through SD-Torus (Semi-Diagonal Torus) (Semi-Diagonal Torus), which realizes distributed forwarding and switching. The key problems such as the structure of isomorphic processing unit in the IP router on-chip system, the selection of the topology of the intrachip interconnection network, the mapping of address lookup and packet switching functions on each processing unit are studied. The system on chip of the IP router is modeled by using the hardware description language SystemC, and by adopting different IP packet traffic model, the performance of the system on the chip of the router under different network scale and different load degree is analyzed. Some key performance parameters, such as system throughput, average delay and delay jitter, are simulated. The simulation results show that the structure has good system performance and expansibility.
【作者单位】：西安电子科技大学计算机学院;
【基金】：国家自然科学基金项目(60976020) 陕西省教育厅科研计划项目(2010JK833)
【分类号】：TP393.02

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