快速以太网物理层中低压高速模数转换器设计研究

发布时间：2018-08-02 11:17

【摘要】：在快速以太网的物理层中，数据接收通路需要一个采样速率为125MHz、分辨率为8比特的模数转换器将从5类非屏蔽双绞线上接收到的MLT_3码信号转换为数字信号，以供后端数字电路模块进行编解码、数据串并转换以及时钟数据恢复等。在综合考虑模数转换器的采样速率和分辨率两个重要参数以后，本论文中的模数转换器采用了具有高速、中高等精度、结构相对简单等特点的流水线结构。基于快速以太网接收器的应用背景，本论文设计了数据接收通路中转换速率为125MHz、分辨率为8比特的流水线模数转换器。设计中采用了双采样、两级运放的电流缓冲式密勒补偿等关键技术，分析了传统流水线模数转换器的非理想性，，介绍了数字校准技术、带隙基准电路和参考源缓冲器等电路模块。流水线模数转换器的设计采用了SMIC0.13um CMOS工艺，差分输入满摆幅为1Vpp，当输入信号频率为1MHz、采样频率为125MHz时，流水线ADC的微分非线性误差DNL峰值为+0.28LSB/-0.18LSB，积分非线性误差INL峰值为+0.25LSB/-0.41LSB，信号噪声比（SNR）为48.2dB，信号噪声失真比（SNDR）为48.0dB，有效位数约合为7.70位，能够满足以太网系统对模数转换器性能的要求。
[Abstract]:In the physical layer of Fast Ethernet, the data reception path requires an analog-to-digital converter with a sampling rate of 125 MHz and a resolution of 8 bits to convert the MLT_3 code signals received from five types of unshielded twisted pair lines into digital signals. For back-end digital circuit module for encoding and decoding, data string parallel conversion and clock data recovery and so on. After considering the sampling rate and resolution of A / D converter, a pipeline structure with high speed, middle and high precision and relatively simple structure is adopted in this paper. Based on the application background of fast Ethernet receiver, this paper designs a pipelined A / D converter with a conversion rate of 125 MHz and a resolution of 8 bits in the data reception path. In the design, the key technologies, such as double sampling and current buffer Miller compensation of two-stage operational amplifier, are used to analyze the non-ideality of the traditional pipeline A / D converter, and the digital calibration technology is introduced. Bandgap reference circuit, reference source buffer and other circuit modules. The pipeline A / D converter is designed using SMIC0.13um CMOS technology. The differential input full swing is 1V pp. when the input signal frequency is 1MHz and the sampling frequency is 125MHz, The peak value of differential nonlinear error (DNL) of pipeline ADC is 0.28LSB-0.18LSB. the peak value of integral nonlinear error (INL) is 0.25LSB-0.41LSB. the ratio of signal to noise is 48.2 dB, the ratio of signal to noise to distortion is 48.0dB, and the effective digit is about 7.70 bits. It can meet the requirements of the performance of the ADC in the Ethernet system.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN792;TP393.11

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