基于FPGA及以太网技术的100G接口板设计

发布时间：2018-10-10 11:32

【摘要】：近年来,随着IT行业的高速发展,高清视频、虚拟化、电子商务、无线3G以及4G网络等各种新兴业务不断涌现,人们对于网络带宽的需求正在飞速增长,而云计算的出现及部署更加速了人们对网络带宽需求的增长,这势必导致网络汇聚节点网络带宽的成倍增长。高端路由器作为在数据中心和骨干网络层使用的关键互联设备,其10G端口已不能满足业务对于带宽的需求,研究和开发支持100G端口的以太网设备就变得十分必要和迫切了。以往的以太网设备,多是以专用的网络处理芯片为主体设计的,而专用芯片的设计不够灵活、移植性不强,而且价格昂贵,导致以太网设备成本高。本文结合可编程逻辑器件设计灵活、可移植性强的特点,采用Altera公司最新StratixV可编程逻辑器件,设计一套以两片FPGA为主体的系统方案,两片FPGA分别进行包处理和流量管理,可实现完善的100G路由转发功能。硬件设计部分对系统的主要功能模块：MPU模块、FPGA模块、CFP模块以及电源和时钟模块进行详细设计。理论研究在参阅了IEEE802.3ba标准及其相关会议文稿的基础上,对100G以太网物理层架构及其实现上进行深入研究,详细阐述64B/66B的编解码、并行自同步扰解码以及PCS层MLD通道分发机制的原理,并用verilogHDL语言对其进行设计,在modelsim上对其各个部分进行仿真,验证逻辑设计的正确性。最后在系统层面上对其进行测试设计,结合100G CFP光模块,用spirent公司的testcenter专业打流测试仪对100G接口板进行实际场景测试,验证系统设计的正确性。
[Abstract]:In recent years, with the rapid development of IT industry, high definition video, virtualization, e-commerce, wireless 3G and 4G network and other emerging services, people's demand for network bandwidth is growing rapidly. The emergence and deployment of cloud computing accelerates the growth of network bandwidth demand, which will inevitably lead to the multiple growth of network bandwidth of network convergence node. As the key interconnection equipment used in data center and backbone network layer, the 10G port of high-end router can no longer meet the bandwidth requirement of service, so it is necessary and urgent to research and develop the Ethernet device which supports 100G port. In the past, most Ethernet devices were designed with special network processing chip as the main body, but the design of special Ethernet chip was not flexible, portability was not strong, and the price was high, which led to the high cost of Ethernet equipment. According to the characteristics of flexible design and strong portability of programmable logic devices, this paper uses the latest StratixV programmable logic devices of Altera Company to design a system with two pieces of FPGA as the main part. The two pieces of FPGA are used for packet processing and flow management, respectively. Can achieve a perfect 100 G routing forwarding function. In the part of hardware design, the main function module of the system is: 1. MPU module, FPGA module, CFP module, power supply module and clock module. On the basis of referring to the IEEE802.3ba standard and the related conference papers, the theoretical research has carried on the thorough research to the 100G Ethernet physical layer architecture and its realization, elaborated the 64B/66B codec in detail, The principle of parallel auto-synchronous scrambling decoding and MLD channel distribution in PCS layer is designed with verilogHDL language. The simulation of each part on modelsim is carried out to verify the correctness of the logic design. Finally, it is tested and designed at the system level. The 100G interface board is tested with the 100G CFP optical module and the 100G interface board is tested by the testcenter professional streaming tester of spirent Company, which verifies the correctness of the system design.
【学位授予单位】：南京理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP393.11

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