基于多片FPGA的双优先级动态调度算法

发布时间：2018-10-19 14:45

【摘要】：针对单片现场可编程门阵列(FPGA)在处理高速网络中海量数据时存在效率低下的问题,结合多处理器的双优先级调度算法,在所构建的多片FPGA并行处理的高速数据采集和处理模型上,提出一种基于多片FPGA的双优先级动态调度算法,并对处于低优先级段的强实时周期任务提出一种最早截止期临界松弛调度(EDCL)算法。根据任务的松弛度确定任务的优先级,若提升时间到达时仍未完成,则将其提升到高优先级段;对软实时周期任务,设置在中优先级段,通过延长当前任务截止期至动态模糊阈值进行调度。实验结果表明,该算法能很好地调度强实时周期任务,保证重要任务的优先执行,并能降低由于抢占造成的软实时周期任务错失率。
[Abstract]:In order to solve the problem of inefficient processing of mass data in high-speed network by single-chip field programmable gate array (FPGA), a multi-processor dual-priority scheduling algorithm is proposed. Based on the high speed data acquisition and processing model of multi-chip FPGA parallel processing, a dual-priority dynamic scheduling algorithm based on multi-chip FPGA is proposed. A critical relaxation scheduling (EDCL) algorithm is proposed for strong real-time periodic tasks with low priority. The priority of the task is determined according to the relaxation degree of the task. If the lifting time is not completed, it is raised to a high priority segment, and the soft real-time periodic task is set in the middle priority segment. By extending the current task deadline to the dynamic fuzzy threshold for scheduling. Experimental results show that the proposed algorithm can effectively schedule strong real-time periodic tasks, ensure priority execution of important tasks, and reduce the miss rate of soft real-time periodic tasks caused by preemption.
【作者单位】：桂林电子科技大学电子工程与自动化学院;桂林电子科技大学计算机科学与工程学院;桂林电子科技大学信息与通信学院;
【基金】：国家自然科学基金资助项目(61163058) 广西自然科学基金资助项目(2011GXNSFB018076) 广西科学研究与技术开发计划项目(桂科攻11107006-21)
【分类号】：TP393.08;TN791

【参考文献】