基于侧信道分析的硬件木马检测平台设计
发布时间：2018-11-09 07:24
【摘要】：硬件木马是嵌入在集成电路中的冗余电路单元，能够在一定条件下激活并导致芯片功能失效或信息泄露，在集成电路设计制造的各个环节都有可能被嵌入这种恶意的木马电路硬件木马的出现给芯片安全性带来严重威胁，其相关检测技术日渐成为信息安全领域的研究热点，得到了国际上的广泛关注 本文主要开展了基于功耗电磁等侧信道分析技术的相关研究工作，首先研究了基于组合逻辑时序逻辑的硬件木马载体电路的设计方法，重点介绍了组合逻辑型硬件木马在ISCAS’89基准电路s713中的植入方法针对应用于IP核版权保护中的时序型硬件木马激活时间不足的问题提出了一种改进结构，基于高级加密标准（Advanced Encryption Standard，AES）算法电路验证了这种结构的有效性仿真结果显示，，这种方法能够在电路面积减少0.123%的基础上使木马的激活时间提高约120倍 在此基础上，设计并实现了基于FPGA的检测平台，提出了包括降噪小信号提取等有关平台的验证与优化方法，设计了硬件木马的检测流程最后介绍了基于侧信道分析的数据处理算法，重点针对主成分分析（Principal ComponentAnalysis, PCA）算法开展研究工作，通过提取基于时序型硬件木马的载体电路在木马激活前后的侧信道信息建立电路的电磁辐射模型，在此基础之上验证了PCA算法对于检测时序型硬件木马的有效性 实验结果表明，基于本文所设计的硬件木马检测平台，PCA算法能够有效检测占电路总面积4%以上的硬件木马电路
[Abstract]:The hardware Trojan is a redundant circuit unit embedded in the integrated circuit, which can be activated under certain conditions and lead to the failure of the function of the chip or the disclosure of information. In the integrated circuit design and manufacture of each link is likely to be embedded in this malicious Trojan circuit hardware Trojan has brought a serious threat to the security of the chip, its related detection technology has become a research hotspot in the field of information security. This paper mainly focuses on the research of power dissipation electromagnetic equal-side channel analysis technology. Firstly, the design method of hardware Trojan horse carrier circuit based on combinational logic sequential logic is studied. This paper mainly introduces the implanting method of combinational logic hardware Trojan in ISCAS'89 reference circuit s713. Aiming at the problem of insufficient activation time of sequential hardware Trojan used in IP core copyright protection, this paper proposes an improved structure. Based on the advanced encryption standard (Advanced Encryption Standard,AES) algorithm circuit, the simulation results show that the structure is effective. This method can reduce the circuit area by 0.123% and increase the activation time of Trojan horse by about 120 times. On this basis, the detection platform based on FPGA is designed and implemented. In this paper, the verification and optimization methods of related platforms, including noise reduction and small signal extraction, are put forward. The detection flow of hardware Trojan horse is designed. Finally, the data processing algorithm based on side channel analysis is introduced, especially for principal component analysis (Principal ComponentAnalysis,). PCA) algorithm, the electromagnetic radiation model of the circuit is established by extracting the side channel information of the carrier circuit based on the time series hardware Trojan horse before and after the Trojan horse is activated. On this basis, the validity of PCA algorithm for detecting sequential hardware Trojan horse is verified. The experimental results show that, based on the hardware Trojan detection platform designed in this paper, PCA algorithm can effectively detect the hardware Trojan circuit which accounts for more than 4% of the total circuit area.
【学位授予单位】：天津大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP393.08
本文编号：2319740
[Abstract]:The hardware Trojan is a redundant circuit unit embedded in the integrated circuit, which can be activated under certain conditions and lead to the failure of the function of the chip or the disclosure of information. In the integrated circuit design and manufacture of each link is likely to be embedded in this malicious Trojan circuit hardware Trojan has brought a serious threat to the security of the chip, its related detection technology has become a research hotspot in the field of information security. This paper mainly focuses on the research of power dissipation electromagnetic equal-side channel analysis technology. Firstly, the design method of hardware Trojan horse carrier circuit based on combinational logic sequential logic is studied. This paper mainly introduces the implanting method of combinational logic hardware Trojan in ISCAS'89 reference circuit s713. Aiming at the problem of insufficient activation time of sequential hardware Trojan used in IP core copyright protection, this paper proposes an improved structure. Based on the advanced encryption standard (Advanced Encryption Standard,AES) algorithm circuit, the simulation results show that the structure is effective. This method can reduce the circuit area by 0.123% and increase the activation time of Trojan horse by about 120 times. On this basis, the detection platform based on FPGA is designed and implemented. In this paper, the verification and optimization methods of related platforms, including noise reduction and small signal extraction, are put forward. The detection flow of hardware Trojan horse is designed. Finally, the data processing algorithm based on side channel analysis is introduced, especially for principal component analysis (Principal ComponentAnalysis,). PCA) algorithm, the electromagnetic radiation model of the circuit is established by extracting the side channel information of the carrier circuit based on the time series hardware Trojan horse before and after the Trojan horse is activated. On this basis, the validity of PCA algorithm for detecting sequential hardware Trojan horse is verified. The experimental results show that, based on the hardware Trojan detection platform designed in this paper, PCA algorithm can effectively detect the hardware Trojan circuit which accounts for more than 4% of the total circuit area.
【学位授予单位】：天津大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP393.08
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