X-DSP中千兆以太网MAC控制器的设计与实现

发布时间：2018-12-06 09:54

【摘要】：以太网技术是计算机网络通信中最重要的技术,它经过四十多年的发展,已经在工业控制、通信系统中得到广泛应用。MAC控制器是以太网的重要设备,完成OSI模型数据链路层中MAC子层的功能。本文以自主研发的多核高性能数字信号处理器X-DSP为背景,设计了一个千兆以太网MAC控制器,为X-DSP提供了一个千兆速率的网络接口。根据X-DSP的性能需求,并通过对以太网MAC子层的深入分析,明确了MAC控制器的功能,设计了千兆以太网MAC控制器总体结构,以及时钟管理方案。采用相互独立的数据通路与配置通路实现MAC控制器与上层逻辑的连接。数据通路中采用基于突发且可并行读写的AXI接口进行数据传输,保证接收、发送数据的高效传输;配置通路采用简化的AXI接口实现对MAC控制器中寄存器的读写操作。为实现MAC控制器10Mbps/100Mbps/1000Mbps的数据传输速率,设计了MII和GMII两种类型的PHY接口;提供地址匹配、哈希表等多种地址过滤方式,采用并行的CRC-32算法用于以太网帧的校验。支持半双工和全双工两种通信模式,半双工模式下采用多路载波侦听/冲突检测(CSMA/CD)的传输机制和背压的流量控制机制;全双工模式下设计了基于暂停帧的流量控制方式。MAC控制器待发送、已接收数据以及相关控制信息采用两个深度为512、位宽为133的异步FIFO进行缓存和同步处理。按模块级和系统级两个层次,分别搭建了验证平台,对MAC控制器的功能以及时序进行了模拟验证。验证以及综合结果表明,MAC控制器的功能正确,满足设计要求。
[Abstract]:Ethernet technology is the most important technology in computer network communication. After more than 40 years' development, it has been widely used in industrial control and communication system. MAC controller is an important device of Ethernet. The function of MAC sub-layer in the data link layer of OSI model is completed. In this paper, a gigabit Ethernet MAC controller is designed based on the multi-core high-performance digital signal processor (X-DSP), which provides a gigabit rate network interface for X-DSP. According to the performance requirement of X-DSP and the analysis of Ethernet MAC sublayer, the function of MAC controller is clarified, and the overall structure of MAC controller of Gigabit Ethernet and the clock management scheme are designed. An independent data path and configuration path are used to realize the connection between the MAC controller and the upper layer logic. The data path adopts AXI interface based on burst and can read and write in parallel to ensure the efficient transmission of receiving and transmitting data. The configuration path uses simplified AXI interface to realize the read and write operation of registers in MAC controller. In order to realize the data transmission rate of MAC controller 10Mbps/100Mbps/1000Mbps, two types of PHY interfaces, MII and GMII, are designed, and a variety of address filtering methods, such as address matching and hash table, are provided. The parallel CRC-32 algorithm is used to verify the Ethernet frame. The half-duplex and full-duplex communication modes are supported. In the half-duplex mode, the transmission mechanism of multi-channel carrier listening / collision detection (CSMA/CD) and the flow control mechanism of back pressure are adopted. In full duplex mode, the flow control mode based on pause frame is designed. The MAC controller is to be sent, the received data and related control information are cached and processed synchronously by two asynchronous FIFO with depth of 512 and bit width of 133. According to the two levels of module level and system level, the verification platform is built, and the function and timing of MAC controller are simulated and verified. The results of verification and synthesis show that the function of MAC controller is correct and meets the design requirements.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP393.11

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