基于FPGA的RapidIO和万兆以太网路由控制器设计

发布时间：2018-12-14 18:05

【摘要】：随着信息社会的发展,人们对计算机技术的高实时性和高可靠性的要求日益增长,加之芯片技术的不断进步,嵌入式计算技术将获得广阔的发展空间和应用前景。目前,嵌入式计算技术已进入工业控制、环境工程、信息家电和个人移动数据处理等诸多领域,尤其是高性能嵌入式计算技术,在国防、航天等重要领域发挥着重要作用。高性能嵌入式分布式集群系统的发展离不开高速总线电路的发展。在以高性能嵌入式计算技术构建的综合化信息处理系统中,为了实现数据的高速通信,采用串行RapidIO高速总线和万兆以太网两种协议分别作为射频前端预处理和后端综合显控处理的数据交换网络,因此,面临两种协议之间的实时数据转换问题。串行RapidIO由于使用高速串行技术,并且拥有可以将多个处理器互联,使计算机集群化,云计算化、内存共享等特点,被广泛运用于嵌入式计算机的芯片间、板间通信互联。目前,在嵌入式计算机领域及通信技术领域,RapidIO已逐渐成为新型多计算机、多处理器、多DSP的互联的首要选择。万兆以太网是一种高速以太网接口,提供10Gbps的以太网带宽的长距离传输,被广泛应用于数据交换中心、数据视频广播等需要高带宽数据的场合,并且可以有效实现网络上大数据量汇聚和链路聚合。本文针对两种协议之间的实时数据转换问题,设计了一个串行RapidIO和万兆以太网之间的路由控制接口,采用硬件设计技术实现了高速实时的数据传输通道,可以被广泛应用于综合信息电子系统,以及作为智能的IO接口模块形式应用于多个前端射频预处理和核心处理机平台中,用以解决嵌入式实时系统和后端任务信息处理系统的大数据实时交换问题,有很高的应用价值。本文的主要工作包括：(1)设计了一个基于FPGA的串行RapidIO和万兆以太网之间的路由控制接口,可在两种协议之间实现数据包转换的流水操作。该接口由一个4×SRIO接口、一个万兆以太网接口和一个用户调度逻辑模块构成,其中用户调度逻辑模块主要进行两部分处理：接收万兆以太网传来的数据包转换为RapidIO邮箱消息与接收RapidIO邮箱消息转换为以太网包。(2)使用RapidIO邮箱消息机制来处理不同协议之间的数据包转换,将接收到的以太网包拆分成若干个消息段(segs),而将接收到的RapidIO邮箱消息组合成以太网包进行发送。使用RapidIO Doorbell作为中断,用来通知接收方发送已完成。在万兆网转RapidIO和RapidIO转万兆网两个方向上,都采用可重传超时错误包的消息发送结构。(3)在接收处理RapidIO邮箱消息时,需要将消息存储在FPGA上,等收齐一组消息后再按照以太网包的格式发送。为了区分消息内容和其他邮箱消息,专门设计了16个邮箱模块来进行多组消息的整合,并通过比对消息长度(Msglen)和消息标识(Msgseg)来检查一组消息是否发送完成。(4)使用物理地址与邮箱地址查找表寄存器组来配置万兆以太网络设备与RapidIO邮箱之间的匹配信息。同时,采用RapidIO的NREAD和NWRITE操作对寄存器进行相应的维护与更改。
[Abstract]:With the development of the information society, people's demands for high real-time and high reliability of computer technology, and the progress of the chip technology, the embedded computing technology will have a wide development space and application prospect. At present, the embedded computing technology has entered the fields of industrial control, environmental engineering, information appliances and personal mobile data processing, especially high-performance embedded computing technology, and plays an important role in the important fields such as national defense and aerospace. The development of high-performance embedded distributed cluster system is based on the development of high-speed bus circuit. in a comprehensive information processing system constructed with high-performance embedded computing technology, in order to realize high-speed communication of data, two protocols of a serial RapidIO high-speed bus and a ten-gigabit Ethernet are adopted as a data exchange network of a radio-frequency front-end pre-processing and a back-end integrated display control process, The problem of real-time data conversion between the two protocols is faced. Serial RapidIO is widely used in inter-chip and inter-board communication of embedded computer due to the use of high-speed serial technology, and it has the characteristics of interconnection of multiple processors, computer clustering, cloud computing, and memory sharing. At present, in the field of embedded computer and communication technology, RapidIO has become the first choice for multi-computer, multi-processor and multi-DSP. The 10-Gigabit Ethernet is a high-speed Ethernet interface, which provides the long-distance transmission of 10Gbps Ethernet bandwidth, and is widely used in the field of data exchange center, data video broadcasting and the like, and can effectively realize the convergence and link aggregation of large data volume on the network. In order to solve the problem of real-time data conversion between two protocols, a route control interface between serial RapidIO and 10 Gigabit Ethernet is designed, and the high-speed real-time data transmission channel is realized by the hardware design technology, which can be widely used in the comprehensive information electronic system. and is applied to a plurality of front-end radio-frequency pre-processing and core processor platforms as an intelligent IO interface module, and is used for solving the problem of large-data real-time exchange of the embedded real-time system and the back-end task information processing system, and has high application value. The main work of this paper includes: (1) designing a routing control interface between serial RapidIO and 10 Gigabit Ethernet based on FPGA, and can realize the flow operation of data packet conversion between the two protocols. The interface consists of a 4-level SRIO interface, a ten-gigabit Ethernet interface and a user scheduling logic module, wherein the user scheduling logic module mainly performs two-part processing: The packet received from the 10 Gigabit Ethernet is converted to the RapidIO mailbox message and the received RapidIO mailbox message is converted to an Ethernet packet. (2) the RapidIO mailbox message mechanism is used for processing data packet conversion between different protocols, and the received Ethernet packet is split into a plurality of message segments (segs), and the received RapidIO mailbox message is combined into an Ethernet packet for transmission. Use RapidIO Doorbell as an interrupt to inform the recipient that the transmission has been completed. The message transmission structure of the retransmission time-out error packet is used in both directions of the 10-mega-net-to-RapidIO and the RapidIO-M-M network. and (3) when the RapidIO mailbox message is received, the message needs to be stored on the FPGA, and after the group of messages is received, the message is sent according to the format of the Ethernet packet. in order to distinguish the message content and other mailbox messages, 16 mailbox modules are specifically designed to complete the multiple sets of messages and check whether a set of messages is sent by a comparison of the message length (Msglen) and the message identity (Msgseg). and (4) using a physical address and an e-mail address lookup table register group to configure the matching information between the ten-gigabit Ethernet network device and the RapidIO mailbox. At the same time, the registers are maintained and changed with the NREAD and NWRITE operations of RapidIO.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP393.11;TP393.05

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