流媒体传输协议的IP核设计
发布时间：2019-05-16 02:22
【摘要】：网络传输的流媒体技术已经被广泛应用到各个领域,现阶段流媒体数据的实时传输主要依赖于操作系统来实现,本论文设计实现了一个脱离主机操作系统、通过网络接口即可独立进行流媒体数据收发的IP核,有效地解决了网络数据在收发过程中对主机处理器和存储器资源的占用和浪费,提升了处理器的工作效率。 流媒体传输协议的IP核设计是以OSI开放系统互联模型为基础,深刻理解网络协议的层次架构之后,采用FPGA自顶而下的模块化设计理念,以网络协议内容为框架,对各协议层进行模块化设计,而物理层部分采用单端口10/100Mbps收发器WJLXT972C. 网络传输流媒体数据要进行应用层、网络层、传输层和数据链路层等各协议层帧头的封装,各协议层模块按功能划分为控制模块和数据通道。前者用多个状态机的状态跳转来协同实现发送与接收控制,后者用FIFO进行数据的存储,利用CRC校验进行数据检错。 整个设计采用Xilinx公司的ISE软件完成,用VHDL语言实现流媒体传输协议的IP核设计,各个协议层模块附有状态跳转图和结果分析图。系统验证采用Virtex-II开发板,通过RJ-45接口与PC端相连,将IP核传输来的流媒体数据在主机端进行数据接收和解码显示验证。
[Abstract]:The streaming media technology of network transmission has been widely used in various fields. At present, the real-time transmission of streaming media data mainly depends on the operating system. In this paper, a separate host operating system is designed and implemented. The IP core of streaming media data receiving and receiving can be carried out independently through the network interface, which effectively solves the occupation and waste of host processor and memory resources in the process of receiving and receiving network data, and improves the working efficiency of the processor. The IP core design of streaming media transmission protocol is based on OSI open system interconnection model, deeply understands the hierarchical architecture of network protocol, adopts the modular design concept of FPGA from top to bottom, and takes the content of network protocol as the framework. The modularization design of each protocol layer is carried out, while the physical layer adopts single port 10/100Mbps transceiver WJLXT972C.. The transmission of streaming media data in the network should be packaged by the application layer, the network layer, the transport layer and the data link layer. Each protocol layer module is divided into control module and data channel according to its function. The former uses the state jump of multiple state machines to realize the transmission and reception control, while the latter uses FIFO for data storage and CRC verification for data error detection. The whole design is completed by ISE software of Xilinx Company, and the IP core design of streaming media transmission protocol is realized by VHDL language. each protocol layer module is equipped with state jump diagram and result analysis diagram. The system is verified by Virtex-II development board, connected with PC through RJ-45 interface, and the streaming media data transmitted by IP core is verified by data reception and decoding display on the host side.
【学位授予单位】：太原理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP393.04
[Abstract]:The streaming media technology of network transmission has been widely used in various fields. At present, the real-time transmission of streaming media data mainly depends on the operating system. In this paper, a separate host operating system is designed and implemented. The IP core of streaming media data receiving and receiving can be carried out independently through the network interface, which effectively solves the occupation and waste of host processor and memory resources in the process of receiving and receiving network data, and improves the working efficiency of the processor. The IP core design of streaming media transmission protocol is based on OSI open system interconnection model, deeply understands the hierarchical architecture of network protocol, adopts the modular design concept of FPGA from top to bottom, and takes the content of network protocol as the framework. The modularization design of each protocol layer is carried out, while the physical layer adopts single port 10/100Mbps transceiver WJLXT972C.. The transmission of streaming media data in the network should be packaged by the application layer, the network layer, the transport layer and the data link layer. Each protocol layer module is divided into control module and data channel according to its function. The former uses the state jump of multiple state machines to realize the transmission and reception control, while the latter uses FIFO for data storage and CRC verification for data error detection. The whole design is completed by ISE software of Xilinx Company, and the IP core design of streaming media transmission protocol is realized by VHDL language. each protocol layer module is equipped with state jump diagram and result analysis diagram. The system is verified by Virtex-II development board, connected with PC through RJ-45 interface, and the streaming media data transmitted by IP core is verified by data reception and decoding display on the host side.
【学位授予单位】：太原理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP393.04
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