高速路由器中并行化调度器的体系结构

发布时间：2019-08-10 07:29

【摘要】：目前路由器不仅要满足传输带宽的需求,还需要保证用户服务质量。业务量管理器是路由器中的一个重要芯片,负责调度网络流,为用户提供服务质量保证。单个业务量管理器所能支持的带宽受限于硬件的工作频率、数据总线、设计工艺等,难以满足高速率接口,如100Gb/s以太网的要求。又由于路由器内部的空间非常拥挤,如果在路由器的一块线卡上部署多个业务量管理器芯片以满足高带宽的需求,将使得线路板体积增大,成本和功耗也相应增大。为提高单个业务量管理器芯片的处理能力,该文设计了一种支持多线程处理的并行化调度器。并行化调度器采用二级调度策略,能够在不提高系统内部时钟频率的基础上,成倍提高业务量管理器的调度速度;而且并行化调度器共享片外存储器,可以充分利用存储器带宽,减少存储器数目。性能评价结果表明:利用支持4线程的并行化调度器实现的业务量管理器的最大支持带宽可提高3倍;相比于部署4个业务量管理器芯片的方案,4线程方案的片内存储开销、逻辑开销和存储器使用数量分别降低了7.1%、36.2%和75%,而且4线程方案的部署空间和存储器功耗开销都降低了75%。
[Abstract]:At present, routers not only need to meet the needs of transmission bandwidth, but also need to ensure the quality of service of users. Traffic manager is an important chip in router, which is responsible for scheduling network flow and providing quality of service assurance for users. The bandwidth supported by a single traffic manager is limited by the working frequency of hardware, data bus, design process and so on, so it is difficult to meet the requirements of high rate interface, such as 100Gb/s Ethernet. Because the internal space of the router is very crowded, if multiple traffic manager chips are deployed on one line card of the router to meet the needs of high bandwidth, the volume of the circuit board will be increased, and the cost and power consumption will also be increased accordingly. In order to improve the processing ability of a single traffic manager chip, a parallel scheduler supporting multi-thread processing is designed in this paper. Parallel scheduler adopts two-level scheduling strategy, which can double the scheduling speed of traffic manager without increasing the internal clock frequency of the system, and the parallel scheduler shares off-chip memory, which can make full use of memory bandwidth and reduce the number of memory. The results of performance evaluation show that the maximum support bandwidth of traffic manager implemented by parallel scheduler supporting 4 threads can be increased by three times. Compared with the scheme of deploying four traffic manager chips, the on-chip storage overhead, logical overhead and memory usage of the 4-thread scheme are reduced by 7.1%, 36.2% and 75%, respectively, and the deployment space and memory power consumption overhead of the four-thread scheme are reduced by 75%.
【作者单位】：清华大学计算机科学与技术系;
【基金】：国家自然科学基金资助项目(61073171)
【分类号】：TP393.05

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