应用于数字DC-DC中的ADC的研究与设计
发布时间：2018-09-19 17:25
【摘要】：随着微电子技术的发展,电子设备中集成电路对电源的要求越来越高,数字电源管理芯片成为研究者关注的热点。模数转换器(Analog to Digital Convert,ADC)作为关键电路模块,决定了数字DC-DC输出电压的性能,对满足数字DC-DC性能要求的ADC进行研究,具有重要意义。通过对拟实现数字DC-DC性能指标的分析,根据其需要量化的模拟量输入范围窄、绝对精度要求高的特点,实现了一款窗口型Flash ADC。首先,分析了传统Flash ADC的结构,针对BUCK型数字DC-DC特性的要求,确定了本论文ADC的设计指标和系统结构,为了减小电路规模,采用将预放大运算前置的结构;其次,采用SMIC180nm的工艺,通过Spectre+matlab仿真器,完成了包括预放大电路、反馈运放、比较器和编码模块的窗口型FlashADC的电路设计和各工艺角仿真。通过设置合理的参数和共模输入电压,在输入电压变化幅值为25.6mV时,用4-bit ADC实现了最低有效位(LSB)为1.6mV的高绝对精度;再次,针对预放大电路中存在的失调会对电路产生较大影响的问题,深入研究了预放大电路的失调消除方法。通过对MOS晶体管衬底偏压与其阈值电压之间关系的仿真分析,发现合理调节衬底偏压,可以改变MOS管的阈值电压,进而达到消除失调的目的。设计中将预放大电路的运算放大器输入对管设计在两个独立的阱中,以便独立调节它们的衬底偏压,数字信号控制着电阻分压网络输出端的衬底电压,当预放大电路出现失调时,在数字信号控制下通过逐次逼近的方法调节输入对管的相对衬底偏压,直至输入对管等效阈值相等,失调得到消除,校准结束。将具有失调电压消除作用的预放大器应用于设计的窗口型FlashADC中,可有效消除电路的失调。在完成整体系统设计仿真的基础上,完成了 FlashADC的版图设计及后仿真。结果表明,在工作电压为3.3V,采样频率为15MHz的条件下,通过在输入端引入失调电压,然后使用本文提出的失调电压消除方法进行校正。仿真结果表明,在不采用失调消除技术时,有效位数只能达到3.208-bit,而在采用失调消除技术之后,有效位数可以达到3.793-bit, SNDR为24.592dB,相较理想值25.84dB损失很小,满足设计要求。
[Abstract]:With the development of microelectronics technology, the demand of integrated circuits for power supply in electronic equipment is becoming higher and higher. Digital power management chip has become a hot spot of researchers. As a key circuit module, analog-to-digital converter (Analog to Digital Convert,ADC) determines the output voltage performance of digital DC-DC. It is of great significance to study the ADC that meets the performance requirements of digital DC-DC. Based on the analysis of the performance index of digital DC-DC, a window type Flash ADC. is realized according to the characteristics of narrow input range and high absolute precision of analog quantity which needs to be quantified. Firstly, the structure of traditional Flash ADC is analyzed. According to the requirements of BUCK type digital DC-DC, the design index and system structure of this paper ADC are determined. In order to reduce the scale of the circuit, the preamplifier structure is adopted. Using SMIC180nm process and Spectre matlab simulator, the circuit design and process angle simulation of window type FlashADC including preamplifier circuit, feedback operational amplifier, comparator and coding module are completed. By setting reasonable parameters and common-mode input voltage, when the amplitude of input voltage is 25.6mV, the high absolute precision of 1.6mV with the lowest effective bit (LSB) is realized by 4-bit ADC. Aiming at the problem that the misadjustment in preamplifier circuit will have a great influence on the circuit, the method of eliminating the misadjustment of preamplifier circuit is studied in detail. Through the simulation analysis of the relationship between substrate bias voltage and threshold voltage of MOS transistor, it is found that the threshold voltage of MOS transistor can be changed by adjusting the substrate bias voltage reasonably, and the misalignment can be eliminated. In the design, the operational amplifier input pair of the preamplifier circuit is designed in two separate wells to adjust their substrate bias voltage independently, and the digital signal controls the substrate voltage at the output end of the resistive partial voltage network. When the preamplifier circuit is misaligned, the relative substrate bias of the input to the tube is adjusted by successive approximation under the control of the digital signal, until the equivalent threshold of the input to the tube is equal, the offset is eliminated, and the calibration is completed. The misalignment of the circuit can be effectively eliminated by applying the preamplifier with offset voltage elimination to the window type FlashADC. On the basis of the overall system design and simulation, the layout design and post-simulation of FlashADC are completed. The results show that when the operating voltage is 3.3 V and the sampling frequency is 15MHz, the offset voltage is introduced into the input and then corrected by using the offset voltage elimination method proposed in this paper. The simulation results show that the effective bit number can reach 3.208-bit without the offset elimination technique, and the effective bit number can reach 3.793-bit and SNDR is 24.592dB, which is less than the ideal 25.84dB loss and meets the design requirements.
【学位授予单位】：西安理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792;TM46
本文编号：2250810
[Abstract]:With the development of microelectronics technology, the demand of integrated circuits for power supply in electronic equipment is becoming higher and higher. Digital power management chip has become a hot spot of researchers. As a key circuit module, analog-to-digital converter (Analog to Digital Convert,ADC) determines the output voltage performance of digital DC-DC. It is of great significance to study the ADC that meets the performance requirements of digital DC-DC. Based on the analysis of the performance index of digital DC-DC, a window type Flash ADC. is realized according to the characteristics of narrow input range and high absolute precision of analog quantity which needs to be quantified. Firstly, the structure of traditional Flash ADC is analyzed. According to the requirements of BUCK type digital DC-DC, the design index and system structure of this paper ADC are determined. In order to reduce the scale of the circuit, the preamplifier structure is adopted. Using SMIC180nm process and Spectre matlab simulator, the circuit design and process angle simulation of window type FlashADC including preamplifier circuit, feedback operational amplifier, comparator and coding module are completed. By setting reasonable parameters and common-mode input voltage, when the amplitude of input voltage is 25.6mV, the high absolute precision of 1.6mV with the lowest effective bit (LSB) is realized by 4-bit ADC. Aiming at the problem that the misadjustment in preamplifier circuit will have a great influence on the circuit, the method of eliminating the misadjustment of preamplifier circuit is studied in detail. Through the simulation analysis of the relationship between substrate bias voltage and threshold voltage of MOS transistor, it is found that the threshold voltage of MOS transistor can be changed by adjusting the substrate bias voltage reasonably, and the misalignment can be eliminated. In the design, the operational amplifier input pair of the preamplifier circuit is designed in two separate wells to adjust their substrate bias voltage independently, and the digital signal controls the substrate voltage at the output end of the resistive partial voltage network. When the preamplifier circuit is misaligned, the relative substrate bias of the input to the tube is adjusted by successive approximation under the control of the digital signal, until the equivalent threshold of the input to the tube is equal, the offset is eliminated, and the calibration is completed. The misalignment of the circuit can be effectively eliminated by applying the preamplifier with offset voltage elimination to the window type FlashADC. On the basis of the overall system design and simulation, the layout design and post-simulation of FlashADC are completed. The results show that when the operating voltage is 3.3 V and the sampling frequency is 15MHz, the offset voltage is introduced into the input and then corrected by using the offset voltage elimination method proposed in this paper. The simulation results show that the effective bit number can reach 3.208-bit without the offset elimination technique, and the effective bit number can reach 3.793-bit and SNDR is 24.592dB, which is less than the ideal 25.84dB loss and meets the design requirements.
【学位授予单位】：西安理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792;TM46
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