X波段低相噪取样DRO的研究

发布时间：2018-01-04 13:29

本文关键词：X波段低相噪取样DRO的研究　出处：《电子科技大学》2016年硕士论文　论文类型：学位论文

【摘要】：为了满足航天探测领域快速发展的要求,军用微波系统的研制工作开始受到很多学者的关注。与此相关的技术很多,其中低相位噪声的取样锁相频率源集合了锁相环路(PLL)和介质振荡器(DRO)两者之长,被广泛应用于空间探测、测量仪器等特定领域。目前大多数生产的锁相介质振荡器(PLDRO)多是依靠工程人员的实践经验完成设计与调试的,缺乏理论上的深度分析和指导。设计上也存在周期长、难度大等实际问题。基于以上现状,为了满足型号任务需求,本题目主要目的是对X波段取样锁相介质振荡器进行研制与实现,旨在对取样鉴相、扩捕电路、稳定判决等难点问题进行深入的理论分析。本文通过ADS软件仿真使介质振荡器电路的设计过程简化,最终满足型号指标需要并对以后的设计工作起到参考作用。本文主要研究设计了一种9.66GHz的取样PLDRO。在研究过程中,首先阐述了锁相环的理论和结构。在环路线性模型的基础上着重分析了相位噪声与稳定性判决,并对环路的锁定与失锁问题进行了介绍。然后对介质振荡器进行理论分析与软件仿真。在设计过程中,先通过电路仿真软件ADS确定直流偏置参数,然后建立了相应的模型并做了模拟调试工作;再利用奈奎斯特稳定性判决进行起振仿真;然后得到相位噪声、谐振频率等仿真结果。最终在取样锁相电路的设计中,计算出环路参数,并选取取样鉴相芯片MSPD2018-H50实现取样锁相环路功能。为了确保此种电路可以长时间可靠工作,还同时选取了运算放大器OP470设计了扩捕扫描电路并对其进行了输出信号仿真。9.66GHz的PLDRO最终功率输出为4.5dBm,在偏离载波1kHz、10kHz、100kHz以及1MHz处的相位噪声分别是-93.5dBc/Hz@1kHz;-97.4dBc/Hz@10kHz;-100.1dBc/Hz@100kHz;-129.5dBc/Hz@1MHz,谐波抑制达到了-59.8dBc@2f0,达到了要求的设计目标。
[Abstract]:In order to meet the rapid development of space exploration areas, development of military microwave system has been the concern of many scholars. The related technology, including sampling phase-locked frequency source with low phase noise collection phase locked loop (PLL) and dielectric resonator oscillator (DRO) of both, is widely used in space exploration and measurement the instrument and other specific areas. At present most of the production of the phase locked dielectric resonator oscillator (PLDRO) is completed by the experience of design and debugging, the lack of in-depth analysis and theoretical guidance. The design also exists in the long period, difficult practical problems. Based on the above situation, in order to meet the needs of the task type, title is the main purpose of the X band phase locked dielectric resonator oscillator was developed and implemented, aimed at the sampling phase, acquisition circuit, analyze the deep theory. The difficult problems such as stability judgment This paper makes the design process of dielectric resonator oscillator circuit is simplified by ADS simulation software, and ultimately meet the needs and model index reference for future design. This paper mainly studies the design of a 9.66GHz PLDRO. sample in the course of the study, first elaborated the PLL theory and structure. Based on the linear model of the loop focuses on the analysis of the phase noise and the stability of the judgment, and loop locked and unlocked problems were introduced. Then the theoretical analysis and Simulation of dielectric resonator oscillator. In the design process, first DC bias parameters were determined by the simulation software of ADS, and then established the corresponding model and make the simulation debugging work; reuse Nyquist stability judgment vibration simulation; and then obtain the phase noise, etc. the simulation results of the resonant frequency. Finally in the design of sampling phase locked circuit, calculate the ring road The parameters, and select the sampling phase detector chip MSPD2018-H50 to realize the PLL function. In order to ensure that the circuit can work reliably for a long time, also selected the OP470 operational amplifier designed to capture scanning circuit and the output signal simulation of.9.66GHz PLDRO to its final power output of 4.5dBm, 10kHz in 1kHz from the carrier, phase. 100kHz and 1MHz noise are -93.5dBc/Hz@1kHz; -97.4dBc/Hz@10kHz; -100.1dBc/Hz@100kHz; -129.5dBc/Hz@1MHz, harmonic suppression reached -59.8dBc@2f0, meet the design requirements.

【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN752

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