谐波抑制系统中分频器及相位误差检测的研究

发布时间：2018-01-06 23:01

本文关键词：谐波抑制系统中分频器及相位误差检测的研究　出处：《东南大学》2015年硕士论文　论文类型：学位论文

【摘要】：在数字广播领域,芯片的高集成度以及低成本逐渐成为主流,因此对于接受机的设计提出了更高的要求。为了提高接收机系统中的射频接收机集成度,其架构广泛采用零中频结构,并且对谐波抑制系统的应用日渐成熟。然而一个高性能的接收机系统需要频率综合器部分提供低噪声的本振信号,因此分频器的设计在接收机应用中起到至关重要的作用,也对为谐波抑制混频器提供本振信号的分频提出了更高的要求。由于电路制造中必然存在失配,进而对有相位要求的信号产生误差,故需要相位误差检测器以及相位误差校正电路以提高接收机系统的性能指标。本文介绍了分频器的种类以及不同种类分频器的工作原理,深入分析应用在吉比特以上速率的电流模逻辑分频器的工作原理,并对近年热门的注入锁定理论基于电流模分频器进行全面的理论分析,随后深入分析分频器中噪声产生的原理,总结出电流模逻辑分频器的设计经验以及理论指导,并纠正有源负电容理论中的一个错误。基于谐波抑制理论和系统工作要求,设计一种改进的超高速预分频器及4分频电路,其中高速预分频器采用去尾电流源及有源负电容技术,工作频率25GHz-5GHz,工作电压1.2V,功耗4mW,FoM值为27.6。用于为谐波抑制系统提供本振信号的高速分频器,工作频率1.6GHz～800MHz,提供6路相位差45。同频信号,工作电压1.8V,电流1.2mA。随后对相位误差检测以及误差校正理论进行分析与研究,设计相位误差检测器以及校正电路。相位误差检测器采用吉尔伯特单元结构,工作频率为400MHz～100MHz,工作电压1.8V,功耗1mA。相位误差校正电路采用数字模拟混合校正方案,数字部分采用8位开关电流相位误差进行校正,模拟部分采用可变有源负电容实现相位误差校正。本文中的所有电路使用SMIC RF 0.18μm CMOS工艺。
[Abstract]:In the field of digital broadcasting, chip with high integration and low cost has gradually become the mainstream, so the design of receiver and put forward higher requirements. In order to improve the receiver system in RF receiver integration, its architecture is widely used zero if structure, and the harmonic suppression application system is becoming more and more mature. However, a high the performance of the receiver system to the frequency synthesizer provides the vibration signal of low noise, so the divider in the receiver application plays a vital role, also for the harmonic suppression mixer provides the vibration signals in the frequency put forward higher requirements. Because the circuit manufacturing inevitable mismatch, resulting in errors on the signal phase requirements, so it needs a phase error detector and phase error correction circuit to improve the performance of the receiver system. This paper introduces a kind of frequency divider And the working principle of different frequency divider, in-depth analysis of working principle of current mode logic divider used in Gigabit above rate, and the recent hot injection locking theory of comprehensive theoretical analysis of current mode frequency divider based on the principle, followed by in-depth analysis of noise generated in the frequency divider, summed up the experience in the design of current mode logic frequency divider the theory and guidance, and correct a wrong active negative capacitance theory. Harmonic suppression theory and system based on an improved design of ultra high speed prescaler and 4 frequency divider circuit, the high speed prescaler with tail current source and active negative capacitance technique, the frequency of 25GHz-5GHz work. Voltage 1.2V, power 4mW, FoM value is 27.6. for providing high speed divider of the vibration signal for harmonic suppression system, frequency from 1.6GHz to 800MHz, offers 6 phase difference with the frequency of 45. letters Number, working voltage 1.8V, current 1.2mA. and the phase error detection and error correction theory analysis and research, design a phase error detector and phase error correction circuit. The detector uses Gilbert unit structure, working frequency is 400MHz ~ 100MHz, voltage 1.8V, power 1mA. phase error correction circuit and analog hybrid digital calibration scheme using digital the 8 switch current phase error correction, the analog part adopts variable capacitor to realize active negative phase error correction circuit using SMIC RF. All 0.18 m CMOS process in this paper.

【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN772

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