支持HART协议的智能两线制仪表专用芯片设计

发布时间：2018-01-07 02:07

本文关键词：支持HART协议的智能两线制仪表专用芯片设计　出处：《沈阳工业大学》2017年硕士论文　论文类型：学位论文

【摘要】：HART协议是目前应用最为广泛的工业现场总线通信协议,这种通信协议基于传统的两线制变送器。两线制仪表又称为回路供电仪表,现场仪表与控制室之间只使用两根线连接,这两根线既是电源线也是信号线,4-20mA的回路电流就是与被测物理量对应的信号。HART协议是将数字信号以FSK形式叠加到4-20mA模拟信号上来实现数字通信的协议,这种数字通信目前主要用于对仪表进行现场标定。两线制仪表的电路通常需要基于专用芯片设计,论文中讨论的芯片就是既能实现两线制仪表功能,又可支持HART协议的芯片,这种芯片目前还没有定型产品。本文介绍了一种基于国内工艺设计的两线制仪表专用芯片,并重点讨论了其中调制电路和解调电路的设计和实现方法。设计以前期完成的基本两线制仪表芯片为基础,通过增加调制解调电路,扩展了原芯片的功能。课题的技术难点在于芯片面积和功耗,简单地将两种芯片的电路集成会导致过大的面积和过高的功耗。论文的主要创新点是提出了一种新的调制电路设计方法,采用了波形合成技术来实现正弦波信号,并通过电流控制方法解决了FSK信号的频率控制问题,与传统方法相比,减小了芯片面积并降低了输出信号波形失真度。在解调电路中,采用开关电容滤波技术减少了芯片的外部元件,采用一种特殊数字电路识别接收到的信号,减小了芯片面积并降低了功耗。设计基于国内BCD工艺实现,通过严格的仿真分析,验证了电路的正确性。首先使用Cadence软件对每个功能模块进行电路设计,然后采用HSPICE对各个模块进行仿真分析,主要包括波形产生电路、比较器、运算放大器、开关电容滤波器和数字控制电路。其中数字控制电路和开关电容滤波器是整个设计的核心,所以对于这两个部分进行了重点分析。最后采用华虹NEC的BCD 0.35μmGE工艺进行版图的绘制,并通过了DRC和LVS。
[Abstract]:The HART protocol is the most widely industrial fieldbus communication protocol, the communication protocol of two wire transmitter. Based on the traditional two wire instrument called the circuit power supply instrument, field instruments and control room use only two wires, the two lines is the power line and signal line, the loop current is 4-20mA with the measured physical quantity signal corresponding to the.HART protocol is the digital signal in the form of FSK added to the 4-20mA analog signal to realize digital communication protocol, this digital communication is mainly used on the instrument calibration circuit. Two wire instrument design based on ASIC chip is usually discussed in this thesis is not only to achieve two wire instrument function, and can support HART protocol chip, this chip is currently no standard products. This paper introduces a two wire instrument design based on domestic technology Table a special chip, and the design of the modulation circuit and demodulation circuit and the realization method is discussed. The basic two wire instrument chip design in the early completion of the foundation, by increasing the modulation and demodulation circuit, extended the original chip. The technical difficulty of the subject lies in the chip area and power consumption, simple circuit integration. Two kinds of chip lead to large area and high power consumption. The main innovation of this paper is to propose a new modulation circuit design method, using waveform synthesis technology to realize the sine wave signal, and through the current control method to solve the control problem of the frequency of the FSK signal, compared with the traditional method, and reduces the chip area and reduce the output signal waveform distortion. In the demodulation circuit, using switched capacitor filter technology to reduce the external components of the chip, by receiving a special digital circuit identification letter No., and reduces the chip area and power consumption. The design and implementation of BCD based on domestic technology, through rigorous simulation analysis, verify the correctness of the circuit. The first to use Cadence software to design the circuit of each module, and the HSPICE of each module of the simulation analysis, including waveform generation circuit, comparator, operational amplifier switched capacitor filter, and digital control circuit. The digital control circuit and switched capacitor filter is the core of the system, so for these two parts are analyzed. Finally the BCD Huahong NEC 0.35 mGE process layout drawing, and through DRC and LVS.

【学位授予单位】：沈阳工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402

【相似文献】