集成电路低功耗扫描测试方法的研究与应用

发布时间：2018-01-07 06:12

本文关键词：集成电路低功耗扫描测试方法的研究与应用　出处：《北京工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着超大规模集成电路的集成度以及复杂性的提高,尤其是片上系统SoC芯片的快速发展,集成电路的测试面临着巨大的挑战。其中,测试时的高功耗已经成为急需解决的关键性问题。研究数据表明,测试期间所产生的功耗通常要比正常工作模式下产生的功耗高很多,过高的测试功耗会导致芯片结构损坏、可靠性下降、成品率降低和测试成本增加等问题。本论文对如何降低集成电路扫描测试功耗(动态扫描测试功耗和静态扫描测试功耗)的问题进行了研究,主要工作包括:1.对集成电路动态扫描测试功耗降低技术进行了研究。分别提出了门控扫描时钟技术和门控组合逻辑技术来降低集成电路动态扫描测试功耗。在门控扫描时钟技术中,通过增加扫描时钟产生模块、修改扫描路径的时钟,把扫描链上的扫描单元分成两个路径,在扫描输出端插入多路选择器,使得扫描链上的扫描时钟频率变成测试时钟频率的一半,而没有增加整个电路的测试时间,从而有效地降低了电路动态扫描测试功耗;在门控组合逻辑技术中,通过增加门控阻隔结构,选取最长关键路径和识别功耗敏感扫描单元,使得组合逻辑在扫描移位操作期间不随扫描单元逻辑值的变化而翻转,从根本上降低动态扫描测试功耗。将门控扫描时钟技术和门控组合逻辑技术组合使用,对ISCAS’89基准测试电路中一组(八个)电路进行测试,结果表明,使电路平均动态扫描测试功耗降低了43.99%,平均扫描测试功耗降低了25.24%。2.对集成电路静态扫描测试功耗降低技术进行了研究。提出了基于传输门降低静态扫描测试功耗的技术。该技术通过使用传输门结构作为门控阻隔结构,并引入低静态功耗控制单元,在没有增加动态扫描测试功耗的同时,使电路产生的漏电流和静态扫描测试功耗最小。通过对ISCAS’89基准测试电路中一组(八个)电路进行测试,并与现有阻隔技术中较好的阻隔结构NOR进行比较,结果表明,传输门结构有着更小的面积开销和时延开销,并能够使待测电路在扫描移位周期中进入低漏电流状态,使电路的平均静态扫描测试功耗降低了12.34%,平均扫描测试功耗降低了6.94%。3.将经过验证的扫描测试功耗降低方法,应用于一款电力线载波通信芯片的扫描测试设计中。基于SMIC0.18μm 1P5M工艺,使用DFT Compiler、TetraMAX和IC Compiler等工具完成了该芯片的扫描测试设计和版图设计。最终,电力线载波通信芯片的测试覆盖率高达98.57%,建立时间为2.10ns,保持时间为0.305ns,动态扫描测试功耗降低37.38%,静态扫描测试功耗降低33.87%。
[Abstract]:With large scale integrated circuit integration and complexity, especially the rapid development of system on chip SoC chip, integrated circuit testing is facing enormous challenges. Among them, the high test power consumption has become a key problem needed to be solved. Research data show that the power consumption generated during the test will usually produce than the normal working mode is much higher, the high test power will lead to damage the chip structure, decrease the reliability, yield reduction and testing cost increases and other issues. This paper on how to reduce the power consumption of integrated circuit scanning test (power dynamic scan test and static scan test power) is researched, the main work includes: technology research on reduction of 1. integrated circuit dynamic scan test power. Put forward respectively gated clock gating technology and combinational logic technology to reduce integration The dynamic test power of scan circuit. In the gated clock technique, by increasing the scan clock generation module, modify the scanning path of the clock, the scanning unit on a scan chain is divided into two paths, insert multiplexer in the scan output, the scanning clock frequency on a scan chain into half test clock frequency, but did not increase the test time of the whole circuit, thereby reducing the dynamic test power of scan circuit effectively; in logic gating combination, through the gated barrier structure increases, select the longest critical path and recognition power sensitive scanning unit, the combination of logical shift operation during the scan flip and did not change with the scanning unit and the logical value of dynamic power reduction scan test from the root. The gated clock gating technology and combination logic technology combined use of ISCAS 89 benchmark circuits in a group ( Eight) circuit test results show that the average dynamic scan test circuit to reduce the power consumption by 43.99%, the average power consumption is reduced by 25.24%.2. scan test on static scan integrated circuit test power reduction techniques were studied. The proposed transmission gate to reduce static power consumption in scan test technology. Based on the technology by using transmission gate structure as gate barrier the structure, and the introduction of low static power control unit, without increasing the power of dynamic scanning test at the same time, so that the circuit generates leakage current and static scan test. Based on the minimum power consumption ISCAS' 89 benchmark circuits in a group (eight) circuit were tested and compared, and the structure of the existing NOR good barrier barrier in the results show that the transmission gate structure has a smaller area overhead and delay overhead, and can measure the circuit in the scan shift cycles into a low leakage current to be State, the average static scan test circuit power consumption is reduced by 12.34%, the average power consumption is reduced by 6.94%.3. scan after scan test verification method to reduce power consumption, the design of scanning test applied to a power line carrier communication chip. SMIC0.18 M technology based on 1P5M, using DFT Compiler, TetraMAX IC and Compiler tools to complete the scan test design and layout design of the chip. In the end, the power line carrier communication chip test coverage up to 98.57%, setting time of 2.10ns, holding time was 0.305ns, 37.38% lower power consumption dynamic scan test, 33.87%. reduces the static power consumption in scan test

【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

【共引文献】