基于UVM的电流监控验证平台设计与实现

发布时间：2018-01-10 22:01

本文关键词：基于UVM的电流监控验证平台设计与实现　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着集成电路设计规模与功能复杂度不断提高,造成验证工作复杂度大幅度提升,验证周期延长到整个芯片开发周期70%的时间,导致验证工作成为集成电路设计的主要瓶颈。因此如何提高验证效率,从而减少验证耗时缩短产品设计周期成为目前数字IC芯片设计最棘手的问题。而抽象层次高、可重用性强、自动化检测程度高的验证系统创建将成为提高验证效率的重要途径。本文通过与传统验证技术进行对比得出层次化验证方法的优势所在,并在此基础上详细对多种新型层次化验证方法进行利弊分析,引出集所有验证方法学优点于一体的UVM验证方法学。基于事务级建模、基于覆盖率驱动以及基于自我检测机制的特点造就UVM验证方法学能够实现覆盖率高、灵活性强、验证过程自动化程度高、效率高以及可重用性强的验证平台。本文对UVM验证环境组件UVC、类库继承关系、UVM运行机制以及UVM中优秀的通讯机制进行深入分析研究,另外还依据待测设计对象电流监控系统的功能特性以及设计结构实现进行验证需求分析,制定验证策略,以UVM验证方法学为指导搭建了基于UVM的验证平台。并采用了基于事务级建模、基于自我检测机制与基于覆盖率驱动等方法相结合的验证手段在制定好的验证情景下对电流监控系统进行详细验证,最终对验证仿真结果与覆盖率进行分析总结。经实践证明,本文以UVM验证方法学为指导搭建的验证平台,在电流监控系统的验证过程中,能够自动化进行数据比较检测,及时定位与报告错误信息,并且以基于覆盖率驱动的方法满足了验证的覆盖率要求,验证效率大幅度提升,同时,该平台可重用性强的特点使得其在不同的项目中可进行复用。
[Abstract]:As the development of integrated circuit design and function of increased complexity, resulting in verification complexity is greatly improved, verification period is extended to the entire chip development cycle of 70% of the time, resulting in validation work has become a major bottleneck of IC design. So how to improve the verification efficiency, so as to reduce the verification time shorten the cycle of product design has become one of the most difficult digital IC chip design. And the high abstract level, strong reusability, high degree of automation testing verification system creation will become an important way to improve the efficiency of verification. By comparing with the traditional verification technology for comparing the hierarchical verification method advantage, and on the basis of detailed on a variety of new hierarchical verification methods advantages and disadvantages analysis leads to UVM verification method all the verification methodology combines the advantages of learning. Transaction level modeling based on flooding based on coverage The dynamic characteristics and self detection mechanism based on creating UVM verification methodology to achieve high coverage, high flexibility, high degree of automation verification process verification platform, high efficiency and strong reusability. The UVM verification environment for UVC component library of inheritance, in-depth analysis of communication mechanism of excellent UVM mechanism and UVM in addition, according to design object current monitoring system to be tested the function characteristics and structure design verification requirements analysis, formulate verification strategies, UVM verification methodology as a guide to build a verification platform based on UVM. And the transaction level modeling based on self detection mechanism based on coverage driven and method based on the combination of the verification methods detailed verification of the current monitoring system in the validation scenario, the final verification of the simulation results and the coverage rate were analyzed. Proved by practice, based on the UVM verification methodology as a guide to build the verification platform, verification process in current monitoring system, automation data detection, positioning and timely report the error, and the method of coverage driven verification based on meet the coverage requirements, verification efficiency is greatly improved, at the same time. The platform of reusable features that make them can be reused in different projects.

【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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