40nm工艺代中道寄生效应及模型研究

发布时间：2018-01-11 08:13

本文关键词：40nm工艺代中道寄生效应及模型研究　出处：《华东师范大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着工艺节点不断降低,版图参数与器件结构参数减小引起的版图邻近效应及寄生效应日趋显著,同时,工艺波动对器件的影响也愈发不可忽略。因此,如何建立一个精确的MOSFET器件模型,使之能够准确描述上述版图与器件结构减小引起的寄生效应,有利于提高纳米电路设计仿真的精确度。基于器件模型的PDK(Process Design Kit,工艺设计包),集全定制电路和半导体工艺于一体,可与模拟软件和验证软件搭载形成一个完整的设计平台,有利于降低设计成本。本文首先分析了 40nm MOSFET寄生电容组成部分,明确各寄生电容的电场线起止范围,归纳各电容所属类别。研究深纳米下的随机掺杂波动、线边缘粗糙度引起的关键尺寸等线宽波动、栅氧等效厚度波动,介绍了光学邻近效应的影响及解决方案。在双介质垂直板电容基础上,结合线边缘粗糙度、等效栅氧化层、过刻蚀等工艺波动及器件剖面的TEM图,考虑了版图布局参数CCS(接触孔至接触孔距离)、CPS(栅至接触孔距离)对寄生效应的影响,建立了一个具有版图相关性的半解析栅至源/漏边缘电容模型。该电容模型与实测数据拟合度在±15%以内,在产业要求的误差范围内,可用于补充改善40nmMOSFET器件模型。寄生效应不仅可以通过模型体现,也可以通过PDK体现。本文基于Virtuoso平台,介绍了 PDK流程以及器件描述格式在电路设计中的作用。按照模型参数要求,对40nm射频器件进行SKILL语言的编写,通过回调函数实现了对器件基本物理结构以及阱邻近效应等寄生效应的处理,实现了 MOS晶体管以及传输线等器件的参数化单元设计。本文基于40nm工艺研究平台,提取了 MOS器件的版图相关性的栅极电容,实现了射频器件的参数化单元,为进一步深入发展40nm工艺提供了研究价值。
[Abstract]:As the technology node decreases, the layout parameters and structural parameters of the device layout reduce proximity effect and parasitic effects caused by the increasingly prominent, at the same time, effects of process variations on devices become more and more can not be ignored. Therefore, how to set up an accurate MOSFET model, which can accurately describe the effect caused by the reduced parasitic layout and device the structure, is conducive to improve the simulation accuracy of nanometer circuit design. The device model based on PDK (Process Design Kit, the process design package), integrates the full custom circuit and semiconductor process, and simulation software and software verification with form a complete design platform, to reduce the cost of design. This paper first analyzes the 40nm MOSFET parasitic capacitance part, clear lines of the parasitic capacitance of the electric field range, including the capacitance category. The deep research of nano random dopant fluctuation, Line edge roughness caused by the key dimensions of linewidth fluctuation, equivalent gate oxide thickness fluctuation, the effect of optical proximity effect and solutions. In the double medium vertical plate capacitor based on the combination of line edge roughness, the equivalent gate oxide layer over etching device and process fluctuation profile TEM, considering the layout parameters CCS (distance contact hole to the contact hole (CPS), distance from the gate to the contact hole) influence on the parasitic effect, set up a model with the edge capacitance leakage layout correlation semi analytical gate to source /. The capacitance model and the measured data fitting degree is less than 15%, the error range of industry requirements in the improved 40nmMOSFET model can be used to supplement the parasitic effects. Through the model can not only reflect, but also by the PDK expression. This paper based on Virtuoso platform and introduces the PDK process and device description format in circuit design. In accordance with the requirements. The parameters of the model, to write SKILL language on the 40nm RF devices, through the callback function to deal with the basic physical structure of the device and the trap effect adjacent parasitic effect, realize the parametric design of unit MOS transistor and transmission line devices. This paper is based on the 40nm technology research platform, from the gate the capacitance of the MOS device layout correlation, realize the parametric unit RF devices, and provides the research value for the further development of 40nm technology.

【学位授予单位】：华东师范大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN386

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