基于CNFET的三值组合电路研究

发布时间：2018-01-12 07:20

本文关键词：基于CNFET的三值组合电路研究　出处：《宁波大学》2015年硕士论文　论文类型：学位论文

更多相关文章： 多值逻辑 CNFET 低功耗 组合电路

【摘要】：二值信号(0,1)在集成电路领域应用较多,但由于它携带的信息量少,导致电路的布线面积增加。为减小电路的布线面积和增加其对数据的处理能力,多值逻辑技术是一种有效方法。多值逻辑电路中每条布线携带的信息量大,输入输出引线数目少,单线携带信息的能力和集成电路的信息密度较高,因此它不仅提高电路空间和时间的利用率,还降低集成电路的生产成本。但是,目前的多值组合逻辑电路大多采用以CMOS工艺为基础的场效应晶体管,所设计出来的组合电路,其结构的复杂性,能量的消耗都大幅度增加,故探讨多值逻辑的低功耗组合电路设计显得尤为重要。因此,通过对碳纳米场效应晶体管(CNFET)和多值逻辑组合电路的研究,以三值逻辑为代表,以组合逻辑电路为研究目标,提出一种基于CNFET的三值组合逻辑电路设计,该设计中利用CNFET新型器件的良好特性,降低了电路功耗,三值组合逻辑电路使电路的信息携带能力得到提高,从而为设计具有高信息密度与低功耗的组合逻辑电路提供了条件。论文将从以下几个部分进行叙述:1、开关—信号理论和三值门电路和文字运算电路设计:深入研究开关—信号理论和CNFET的结构特点,并根据此理论和特点设计基于CNFET的三值门电路和文字运算电路,为设计后续基于CNFET的三值组合逻辑电路奠定基础。2、基于CNFET的三值编译码器设计:分析原有的三值编译码器原理和CNFET的结构特性,以多值逻辑组合电路为基础,结合开关信号理论和文字运算电路的特点,设计基于CNFET的三值编译码器:1T-2B编译码、2T-3B编译码器。3、基于CNFET的多位三值比较器设计:分析三值比较器工作原理,根据多值逻辑电路的设计思想,设计带有编译码器的两位三值比较器,并结合多位比较原理设计基于CNFET的多位三值比较器。4、基于CNFET的三值逐次比较型模数转换器(ADC)设计:分析三值逐次比较器的工作原理,引入三值电容阵列和多束编译码器电路,设计具有三值采样与输出的多值逻辑电路,最终实现基于CNFET的三值逐次比较型ADC。对上述所设计的组合电路进行HSPICE模拟分析,验证所有组合电路的逻辑功能,然后与不同设计方法的组合电路进行功耗和速度比较,验证其电路的高速低功耗特性。
[Abstract]:Two valued signal (0,1) is widely applied in the field of integrated circuits, but because of the amount of information it carries less lead wiring area increased. As the circuit wiring area reduction circuit and increase the data processing ability, multi valued logic technology is an effective method. The multi value information carried by the amount of each wiring logic circuit in large, input and output leads the number of small, high density single information information carrying capacity and the integrated circuit, so it can not only improve the circuit ratio of space and time, but also reduce the production cost of an integrated circuit. However, the current multi valued combinational logic circuit mostly adopts the field effect transistor is based on the CMOS process, combination the circuit is designed, the complexity of its structure, the energy consumption is greatly increased, so the design of low power combination circuit of multiple valued logic is very important. Therefore, based on the carbon nanotube field effect Transistor (CNFET) and study the multi valued logic combination circuit, three valued logic is represented, with a combinational logic circuit as the research object, this paper puts forward a design value of three combinational logic circuit based on CNFET, using the good properties of CNFET in the design of new devices, reduce power consumption, the three value of combinational logic circuit circuit information carrying capacity can be improved, so as to provide the conditions of combinational logic circuit with high information density and low power design. The thesis will be from the following parts: 1, the switch signal theory and the three value gate circuit and text arithmetic circuit design: structural features in-depth study of the switch signal theory and CNFET. And according to the theory and characteristics of the design of CNFET three value gate circuit and operational circuit based on the text, for the subsequent design based on CNFET three combinational logic circuits to lay the foundation for.2, CNFET three compiler based on value Decoder design: analysis of the structure characteristics of CNFET codec principle and the original value of three, with the combination of multiple valued logic circuits based on switch signal theory, combining the characteristics of text and arithmetic circuit, design of CNFET codec based on three values: 1T-2B codec, 2T-3B codec.3, CNFET value of more than three based on the analysis of three values: comparator design principle of comparator, according to multiple valued logic circuit design, the design of a two bit codec three value comparator, and combined with a number of more than three comparison principle CNFET design value comparator based on.4, based on the CNFET value of three successive type analog-to-digital converter (ADC) design: three the working principle of successive values of the comparator, the introduction of the three capacitor array and multi beam decoder circuit design with three sampling value and the output of the multiple valued logic circuit, finally realizes the CNFET value by three times compared to ADC. based on The design of the combinational circuit is simulated by HSPICE, and the logic functions of all combinational circuits are verified. Then, the power and speed of the combinational circuits with different design methods are compared to verify the high speed and low power consumption of the circuit.

【学位授予单位】：宁波大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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