网络芯片物理编码子层关键电路的设计及验证

发布时间：2018-01-12 16:43

  本文关键词：网络芯片物理编码子层关键电路的设计及验证　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

  更多相关文章： 网络芯片 光纤通道 交换机芯片 物理编码子层 SoC

【摘要】：随着互联网技术的快速发展,人类的生活越来越离不开网络。在生活服务等相关领域,无时无刻都要进行信息之间的传输。而网络芯片,在其中一直扮演着重要的角色。目前,对网络芯片的研究中,由于编码校验是数据进行可靠通信的保障,编码校验的效率也是决定芯片面积的重要因素,因此,对于网络芯片中物理编码子层的研究越来越重要。因而,本课题基于对一种网络芯片——光纤通道交换机芯片物理编码子层的研究,基于光纤通道技术的优势,并且采用SoC设计流程,完成了物理编码子层关键电路的设计验证工作,并且实现了可复用IP的设计。本文主要完成的工作包括:1.在设计初期,深入研究了相关基础理论,包括物理层结构和光纤通道技术。在深入理解光纤通道协议和物理编码子层功能的基础上,对该芯片物理编码子层的编码和校验算法进行了研究。综合各方面因素,探究适合光纤通道交换机芯片的编码技术和校验算法。2.基于光纤通道协议,采用当前SoC设计技术,分析了光纤通道交换机芯片的体系架构,提出了适合片上系统设计的光纤通道交换机芯片PCS关键电路具体功能特性要求。根据PCS模块的具体功能,提出了PCS关键电路的设计方案,分别从发送和接收两部分详细介绍了各个子模块的设计。发送部分的设计中,实现了8B/10B的编码、发送缓冲区以及伪随机码产生器的设计;接收部分的设计中,实现了8B/10B的解码、接收弹性缓冲区、Comma的检测和校准以及CRC校验等子模块的设计,最终实现了PCS模块的设计。并且基于光纤通道交换机芯片的研究,本文提出了一种可复用的PCS关键电路的设计技术。3.在模块设计实现后,进行了PCS关键电路的模块级功能仿真、系统级虚拟平台仿真验证以及FPGA的实现。模块级仿真中,首先,根据需求规范、功能规范等编写验证规范,编写测试项;然后根据策划的验证项,编写测试用例,对模块进行了验证。系统级虚拟平台验证中,通过添加不同的总线功能模型,构成交换机芯片工作所需的最小虚拟系统;然后在交换机芯片其他外设接口上,通过编写相应的测试模型,模拟该外设的输入和输出操作,在虚拟的验证环境中完成仿真验证。FPGA实现中,主要是通过综合优化,对其资源和功耗进行了分析。最终实现了PCS关键电路的仿真和验证。
[Abstract]:With the rapid development of Internet technology, the human life is more and more cannot do without the network. The service life and other related fields, to transmit information between every hour and moment. And the network chip, has played an important role in them. At present, the research of network chip, because the encoding check is data for reliable communication security check encoding efficiency is an important factor determining the chip area, therefore, is very important for studying the physical network layer encoding chip more and more. Therefore, the research on a network switch chip -- physical encoding chip sub layer based on fiber channel technology based on the advantages of using SoC and design complete the design process, verification of the key circuit physical layer encoding, and realizes the design of reusable IP. The main work includes: 1. in the design stage, Deep research on the related basic theory, including the physical layer structure and fiber channel technology. Based on deep understanding of the fibre channel protocol and physical layer encoding function, encoding and calibration algorithm of the physical layer encoding chip was studied. Various factors, to explore suitable for fiber channel switch chip encoding and calibration technology.2. algorithm based on fibre channel protocol, using the SoC design technology, analyzes the architecture of fiber channel switch chip, proposed requirements for specific functional characteristics of key circuit fiber channel switch chip PCS system on chip design. According to the specific function of the PCS module, put forward a design scheme of PCS key circuit, respectively, from the sending and receiving the two part introduces the design of each sub module. The design of the transmit part, implementation of the 8B/10B encoding, sending buffer and pseudo random code Generator design; design of the receiving part, realize 8B/10B decoding, receiving elastic buffer, Comma testing and calibration and CRC check module design, finally realizes the design of PCS module. And based on fibre channel switch chip, this paper presents a reusable PCS key circuit the design of.3. technology in the design and Realization of the module, the module function simulation PCS key circuit, system level simulation of virtual platform and the implementation of FPGA. The module level simulation, firstly, according to the requirements of specifications, functional specifications written verification specification, write test items; then according to the validation plan, write test case the module was tested, the system level virtual platform, by adding different bus function model, a minimum system for the virtual switch chip work; then in the switch chip Other peripheral interface, through the preparation of the corresponding test model, analog input and output operation of the peripherals, in a virtual environment to verify the complete simulation.FPGA implementation, mainly through the comprehensive optimization of its resources and power consumption are analyzed. Finally the simulation and verification of PCS key circuit.

【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402;TN929.11

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本文编号：1415118