一种新型CMOS亚阈值四象限模拟乘法器的研究与设计

发布时间：2018-01-13 17:23

本文关键词：一种新型CMOS亚阈值四象限模拟乘法器的研究与设计　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着集成电路技术的高速发展,芯片的规模越来越大、处理能力越来越强,功耗的问题也越来越突出,特别是在便携式电子设备上,由于电池的体积和重量不能做的太大,而续航时间却要求更长,所以低功耗的电路设计成为现在集成电路设计的一个重要方向。不论是在便携式电子设备中的通讯模块中,还是在一些需要数学运算的电路单元中,模拟成乘法器都是很重要的模块。它经常应用于调制、解调、混频、鉴相以及数学运算单元中。因此设计功耗更小精度更高的模拟乘法器具有很重要的意义。本文设计了一个全新结构的亚阈值四象限模拟乘法器,这种新结构对乘法器的性能带来很多好处。第一,不同于传统的吉尔伯特型乘法器,它的核心结构是由电流镜构成,通过衬底驱动技术和电流镜来实现乘法功能,同时衬底驱动也增加了输入的线性范围;第二,通过向量矩阵相乘的结构来实现差分四象限的乘法,这一结构还便于对乘法器进行扩展;第三,通过与CMOS工艺兼容的准浮栅技术来实现输入信号的衰减以及和直流偏置电压的叠加,这不仅增加输入信号的线性范围同时还能够保证共模信号的稳定;第四,该乘法器工作在亚阈值区域并且采用的是低电源电压,所以功耗很低;第五,它的输入输出端口是电压模式,便于集成在电路中,而它的乘法运算却是电流模式,所以又有着更快的速度。本文中亚阈值四象限模拟乘法器的电路设计采用的是0.18?m的TSMC工艺库,仿真工具是Cadence5.10.41。采用1V低电源电压供电,由于工作在亚阈值区域,整个乘法器的总电流不大于100nA,因此功耗不大于0.1?W,由于采用了衬底驱动以及准浮栅技术,该乘法器的输入线性范围可达300mV,输入线性误差小于3%,总谐波失真为1.05%,在偏置电流为30nA时,乘法器的两组输入端中最差的-3dB带宽也可达1.3MHz。该乘法器与吉尔伯特型的亚阈值模拟乘法器相比,有着带宽更大、输入线型范围更大、电路规模更小、结构扩展更灵活的优势,因此在低功耗模拟电路设计方面有着更大的潜力。
[Abstract]:With the rapid development of integrated circuit technology, the scale of the chip is becoming larger and larger, the processing power is more and more powerful, the problem of power consumption is more and more prominent, especially in the portable electronic equipment. Because of the size and weight of the battery can not be done too large, and the duration of the battery is required to be longer. Therefore, low power circuit design has become an important direction of integrated circuit design, whether in the communication module of portable electronic devices or in some circuit units that require mathematical operation. Analog multiplier is an important module. It is often used in modulation, demodulation and mixing. Therefore, it is very important to design analog multiplier with lower power consumption and higher precision. In this paper, a novel sub-threshold four-quadrant analog multiplier is designed. This new structure brings many benefits to the performance of the multiplier. First, unlike the traditional Gilbert multiplier, its core structure is composed of current mirrors. The multiplication function is realized by substrate driving technology and current mirror, and the linear range of input is increased by substrate driving. Secondly, the multiplication of the difference quadrant is realized by the structure of vector matrix multiplication, which is also convenient to extend the multiplier. Thirdly, the quasi-floating gate technology compatible with CMOS process is used to realize the attenuation of input signal and the superposition of DC bias voltage. This not only increases the linear range of input signal, but also ensures the stability of common-mode signal. 4th, the multiplier operates in the sub-threshold region and uses a low power supply voltage, so the power consumption is very low; 5th, its input and output port is voltage mode, easy to integrate in the circuit, and its multiplication is current mode. So there is a faster speed. In this paper, the circuit design of the sub-threshold four-quadrant analog multiplier is 0.18? M's TSMC process library, the simulation tool is Cadence 5.10.41. 1V low power supply voltage is used, because it works in the sub-threshold region. The total current of the whole multiplier is not greater than 100 na, so the power consumption is not greater than 0.1? Due to the use of substrate drive and quasi-floating gate technology, the input linearity range of the multiplier can reach 300mV, the input linearity error is less than 3 and the total harmonic distortion is 1.05%. When the bias current is 30nA, the worst -3dB bandwidth of the two groups of inputs of the multiplier can also reach 1.3 MHz. The multiplier has a larger bandwidth than the Gilbert subthreshold analog multiplier. Because of the advantages of larger input line, smaller circuit size and more flexible structure expansion, it has more potential in low power analog circuit design.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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