基于verilog的小数分频器的设计

发布时间：2018-01-14 07:24

本文关键词：基于verilog的小数分频器的设计　出处：《北京工业大学》2015年硕士论文　论文类型：学位论文

更多相关文章： 频率综合器 小数分频器 Verilog FPGA

【摘要】：随着集成电路的迅猛快速发展,频率综合器在电路中所起的作用显得越来越重要。众所周知,小数分频器作为频率综合器的重要组成部分,其性能、功耗等指标决定了一个频率综合器的频率合成精度。具体来看,小数分频器对于频率综合器的输出精度,相位噪声,锁定时间等性能有重要影响。本文通过具体数据分析了当前集成电路发展过程中数字电路所起的重要作用,并且着重介绍了频率综合器的研究现状,说明了小数分频器是当今数字电路研究中一个重要研究方向。本文通过分析当前小数分频器研究领域中几种主要的电路实现形式,发现尚未有利用纯数字电路实现的小数分频器。故本文在双模前置小数分频器的基础上,提出了一种通过数字电路实现的可编程的小数分频电路。本文提出了数字电路实现的可编程的小数分频器的算法。分析了现有的小数分频器的算法。提出了本小数分频器的参数计算方法,即逐次逼近的参数计算方式。分析了误差成因,设计了控制误差的方法。通过实例展示了分频参数的计算过程。本文设计实现了小数分频器的参数计算模块以及FPGA分频模块。其中包括浮点加法器、浮点乘法器、整数除法器等模块。程序通过verilog语言实现。本文对设计的小数分频器进行了仿真及原型验证。包括小数分频电路的参数计算单元与整体电路仿真,小数分频器FPGA原型验证。仿真结果及逻辑分析仪测试结果均表明电路达到了设计要求。小数分频器的误差可以控制在以10E-9以内。
[Abstract]:With the rapid development of integrated circuits, frequency synthesizer plays an increasingly important role in the circuit. As we all know, fractional frequency divider is an important part of frequency synthesizer. Power consumption and other indicators determine the frequency synthesis accuracy of a frequency synthesizer. Specifically, the frequency synthesizer output accuracy, phase noise of the fractional frequency synthesizer. This paper analyzes the important role of digital circuits in the development of integrated circuits through specific data, and emphatically introduces the research status of frequency synthesizers. It shows that fractional frequency divider is an important research direction in digital circuit research. This paper analyzes several main circuit realization forms in the field of fractional frequency divider research. It is found that there is no decimal frequency divider realized by pure digital circuit. A programmable fractional frequency divider realized by digital circuit is proposed in this paper. The algorithm of programmable fractional frequency divider realized by digital circuit is presented, and the existing algorithm of fractional frequency divider is analyzed. The parameter calculation method of the frequency divider. That is, the parameter calculation method of successive approximation. The cause of error is analyzed. The method of controlling error is designed, and the calculation process of frequency divider parameter is demonstrated by an example. The parameter calculation module of fractional frequency divider and the FPGA frequency division module are designed and implemented in this paper, including floating-point adder. Floating-point multiplier. Integer divider and other modules. The program is implemented by verilog language. The design of the fractional frequency divider is simulated and prototype verified, including the fractional frequency divider parameter calculation unit and the overall circuit simulation. FPGA prototype verification of fractional frequency divider. Simulation results and logic analyzer test results show that the circuit meets the design requirements. The error of fractional frequency divider can be controlled within 10E-9.
【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN772

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