一种高速高精度时钟占空比稳定电路

发布时间：2018-01-15 15:37

本文关键词：一种高速高精度时钟占空比稳定电路　出处：《微电子学》2017年05期 　论文类型：期刊论文

【摘要】：设计了一种高速高精度的时钟占空比稳定电路。采用全差分连续时间积分器将时钟占空比量化为电压信号,积分器对占空比偏差的累积效应可使电路达到很高的调整精度。采用跨导运算放大器将电压信号转换为电流信号,并加载到输入时钟缓冲器上,改变其输出时钟的直流电平,从而调整输出时钟的占空比,避免了调整输出时钟上升/下降沿带来的较大抖动。采用TSMC 0.18μm CMOS工艺进行设计,电源电压为2V。当输入差分时钟频率为1.6GHz时,可以将占空比范围为20%~80%的输入时钟信号的占空比均调节至(50±0.5)%,且输出时钟抖动小于159.398fs,适用于超高速的信号处理系统。
[Abstract]:A high speed and high precision clock duty cycle stabilization circuit is designed, and the clock duty cycle is quantized to voltage signal by using a fully differential continuous time integrator. The accumulative effect of duty cycle deviation of integrator can make the circuit achieve a high precision. The voltage signal is converted into current signal by transconductance operational amplifier and loaded into the input clock buffer. The duty cycle of the output clock is adjusted by changing the DC level of its output clock. The TSMC 0.18 渭 m CMOS process is used to design the output clock, which avoids the big jitter caused by adjusting the rising / falling edge of the output clock. The power supply voltage is 2 V. when the input differential clock frequency is 1.6 GHz, the duty cycle of the input clock signal with duty cycle range of 20% and 80% can be adjusted to 50 卤0.5%. The output clock jitter is less than 159.398fs, which is suitable for super high speed signal processing system.
【作者单位】：合肥工业大学微电子设计研究所;
【基金】：安徽省科技攻关项目(JZ2014AKKG0430) 中央高校基本科研业务费专项资金资助项目(2014HGCH0010)
【分类号】：TN432
【正文快照】： 0引言随着集成电路的不断发展,系统对高速时钟信号的要求越来越高,占空比成为衡量时钟信号的一个重要指标。占空比为50%表示高电平时钟周期的宽度等于低电平时钟周期的宽度。特别是在数据进行双采样的情况下,即时钟的上升沿和下降沿均采样时,保证时钟的占空比为50%是保证系统

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