适用于多通道生物信号采集系统的增量型Sigma-Delta ADC设计

发布时间：2018-01-16 03:33

本文关键词：适用于多通道生物信号采集系统的增量型Sigma-Delta ADC设计　出处：《浙江大学》2015年硕士论文　论文类型：学位论文

【摘要】：当前,植入式和便携式生物医疗仪器已经逐渐进入了人们的视野,而多通道生物信号采集系统则是其中的核心模块。为了满足多个信号采集通道、高信号还原性能和微型化等设计要求,本文提出了适用于多通道生物系统采集系统的高精度低功耗增量型Sigma-Delta ADC。设计方案主要包含增量型Sigma-Delta调制器及数字抽取滤波器的设计。与传统Sigma-Delta调制器不同的是,增量型设计中需要考虑额外的复位信号和过采样率等限制条件。综合考虑系统需求和不同结构的性能,本文采用了3阶单比特量化CIFF结构。在系统建模仿真中,为了更为接近实际情况,噪声和积分器中运放的非理想因素都被加入到理想模型之中。噪声包含热噪声和闪烁噪声两部分,运放中的非理想因素包括DC增益、增益带宽积(Gain Bandwidth, GBW)和摆率(Slew-Rate, SR)等。在电路实现设计中,采用了一级电流镜结构来实现积分器中的运放,且其中采用电流消耗(Current Starvation)技术和电阻补偿技术来提升运放增益和带宽等性能,使运放能更为稳定地工作。调制器中采用了斩波调制技术来抑制低频闪烁噪声。为解决低电源电压所导致的开关非线性问题,采用了时钟电压提升技术。仿真表明在幅值为-12dB,频率为4kHz的正弦波输入下,调制器的信号噪声失真比(Signal-to-Noise and Distortion Ratio, SNDR)达到了96.9dB,功耗和品质因素(Figure of Merit, FOM)分别为40μW和435fJ/conversion-step。此外,本文还完成了由级联梳状(Cascaded of Integrators Comb, CIC)滤波器和两级半带滤波器组成了数字抽取滤波器的设计。仿真结果表明,本文所设计的数字滤波器能够完成降采样和滤波器的功能,并且不影响调制器输出信号的性能。
[Abstract]:At present, implantable and portable biomedical devices has gradually entered people's field of vision, and multi-channel biological signal acquisition system is one of the core modules. In order to meet the needs of multiple signal acquisition channels, high performance and miniaturization of signal design, is proposed in this paper is suitable for multi-channel biological systems acquisition system with high precision and low the power consumption increment Sigma-Delta ADC.
The design scheme includes incremental Sigma-Delta modulator and digital decimation filter. Different from the traditional Sigma-Delta modulator is considering additional reset signal and the oversampling rate restrictions require incremental design. Considering the system requirements and different structure performance, this paper adopts 3 order single bit quantization CIFF structure in the system. Modeling and simulation, in order to more close to the actual situation, the non ideal factors of noise and the op amp integrator were added to the ideal model. The noise consists of two parts of thermal noise and flicker noise, non ideal factors including DC operational amplifier gain, gain bandwidth product (Gain Bandwidth, GBW) and slew rate (Slew-Rate, SR).
In circuit design, using a current mirror structure to achieve the integrator amplifier, and the current consumption (Current Starvation) technology and resistance compensation technology to improve the amplifier gain and bandwidth performance, which can work stably for more operational amplifier. The modulator using chopper modulation technique to suppress the low frequency flicker noise. In order to solve the nonlinear problem caused by switching to low voltage, the clock voltage lift technique. The simulation shows that the amplitude of -12dB, frequency of sine wave input 4kHz, the signal to noise and distortion ratio (Signal-to-Noise and Distortion Ratio, SNDR) reached 96.9dB, and the power quality factor (Figure of, Merit, FOM) 40 W and 435fJ/conversion-step. respectively.
In addition, this paper also completed by the CIC (Cascaded of Integrators Comb, CIC) design consists of a digital decimation filter filter and two stage half band filter. The simulation results show that the digital filter is designed in this paper can complete the down sampling and filter function, and does not affect the performance of the modulator output signal.

【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN761;TN713

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