内建自测试march算法的优化研究

发布时间：2018-01-16 06:13

本文关键词：内建自测试march算法的优化研究　出处：《安徽大学》2015年硕士论文　论文类型：学位论文

更多相关文章： 内建自测试 SRAM 故障模型 March算法

【摘要】：时至今日,随着超大规模电路和超深亚微米工艺等相关技术日趋成熟,与之而来的问题愈发突出,存储器良品率已无法满足工业生产需要。目前芯片的测试成为制约芯片发展的一大瓶颈,由于半导体工艺提高测试难度成本增加,集成电路自动测试机(Automatic Test Equipment)测试已无法满足常规测试需求,为了解决测试问题,关于芯片的内建自测试BIST研究越来越深入。在片上系统(SOC)的微电子应用中大容量嵌入式存储器对内建自测试的依赖愈加突出。由于嵌入式存储器难以从芯片管脚访问,从内部测试恰好解决此问题。对测试时所检测到的故障模型尽可能大面积覆盖,提高良品率促进工业生产。所以,有效的故障模型,有效的测试算法及其实现是嵌入式存储器内建自测试设计的关键所在。本篇论文主要针对时下内建自测试BIST和相关算法优化的研究。本文首先介绍目前测试技术的发展,然后对静态随机存储器SRAM、故障类型进行详细说明,随后详述了MBIST工作流程。最后重点阐述了March算法及其变种,详细分析解读了相关故障模型的原因和解决途径。在目前常用算法March C-的基础上提出自己的新算法March C-D,对March C-无法覆盖的伪读破坏故障DRDF进行了良好的覆盖,并详细分析此算法针对相关故障进行测试工作的过程,得到理论上的验证。最后基于Modelsim平台进行仿真验证March C-D算法的正确性和可行性。此改进算法有更高的覆盖率,并降低MarchC算法检测故障时的重复率。对进一步提高芯片的检测的良品率有显著效果。
[Abstract]:Today, with the development of ultra-large scale circuits and ultra-deep submicron technology, the problems become more and more serious. The memory quality rate can not meet the needs of industrial production. At present, chip testing has become a major bottleneck restricting the development of chips, because of the semiconductor process to increase the cost of difficult testing. IC automatic Test equipment testing can not meet the requirements of conventional testing, in order to solve the test problem. The research on built-in self-test BIST is getting deeper and deeper. System on Chip (SOC). Because embedded memory is difficult to access from chip pin, the dependence of embedded memory on built-in self-test is more and more prominent in microelectronic applications. From the internal test to solve this problem. The fault model detected during the test as much as possible coverage, improve the rate of good products to promote industrial production. Therefore, effective fault model. Effective test algorithm and its implementation are the key of embedded memory built-in self-test design. This paper mainly focuses on the research of built-in self-test BIST and the optimization of related algorithms. Firstly, this paper introduces the current test. The development of trial technology. Then the static random access memory (SRAM), the fault type is described in detail, and then the MBIST workflow is described. Finally, the March algorithm and its variants are described emphatically. The causes and solutions of the related fault models are analyzed in detail. On the basis of March C-, a new algorithm, March C-D, is proposed. The pseudo read failure DRDF which can not be covered by March C- is well covered, and the testing process of this algorithm for related faults is analyzed in detail. Finally, the correctness and feasibility of March C-D algorithm are verified by simulation based on Modelsim platform. This improved algorithm has higher coverage. It also reduces the repetition rate of MarchC algorithm for detecting faults, which has remarkable effect on further improving the rate of good products in chip detection.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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