基于硅通孔连接的三维集成电路测试方法研究

发布时间：2018-01-16 08:28

本文关键词：基于硅通孔连接的三维集成电路测试方法研究　出处：《清华大学》2015年博士论文　论文类型：学位论文

【摘要】：如今随着CMOS技术的迅速发展,集成电路的集成度越来越高,摩尔定律已经进入了一个瓶颈时期。基于硅通孔连接的三维集成电路,凭借其低延迟、低功耗以及支持混合工艺技术等优点,倍受业界青睐,成为了延续摩尔定律的一个重要解决方案。然而,三维集成电路在可以大规模生产,并进入市场之前,还需要克服一系列挑战,其测试问题是这些挑战中不可忽视的一项,甚至被称为“第一大挑战”,而这“第一大挑战”,主要包括三大难点:测试过热、测试成本高以及缺少针对三维封装特性优化的测试工具或EDA软件。本文针对基于硅通孔连接的三维集成电路测试的三大难点,提出了四种对应的优化策略,主要内容和创新点如下:?针对测试过热以及测试成本高这两大难点,本文提出了基于热驱动的测试策略。该策略包括一种新的扫描树测试结构,以及测试向量排序算法。基于三维集成电路扫描树测试结构,可以有效的降低三维集成电路的测试时间,压缩测试数据,从而优化测试成本,而结合测试向量排序算法之后,可以在降低测试成本的同时,有效的降低电路热点区域的温度,解决测试过热的问题。?针对测试成本高的难点,本文提出了基于三维集成电路绑定中和绑定后测试成本优化策略。与以往测试成本模型不同的是,我们不仅考虑测试时间,还考虑硅通孔数目对测试总成本的影响。该优化策略通过改变三维集成电路的堆叠次序,并优化TAM(测试访问机制)带宽的分配,最小化其测试成本。?同样针对测试成本高的难点,本文又从三维集成电路绑定前测试的角度出发,提出了对应的优化策略。该策略利用了核分割技术,并结合一种优化算法,在优化绑定前测试成本方面,有着很好的效果。?针对缺少三维优化的测试工具或EDA软件以及测试成本高这两大难点,本文引入了先进的双速测试仪工具,并在这之上提出了双速TAM测试优化策略,这样既可以引入一种针对三维封装特性优化的测试工具,又降低了电路的测试成本,达到“一箭双雕”的效果。
[Abstract]:Now with the rapid development of CMOS technology, the integration degree of integrated circuit is more and more high, Moore's law has entered a bottleneck period. Three dimensional integrated circuits based on silicon vias connected, with its advantages of low power consumption and low delay, support mixed technology, favored by the industry, has become an important solution to continue Moore's law. However, the three-dimensional integrated circuit in mass production, and before entering the market, also need to overcome a series of challenges, the test problem can not be ignored one of these challenges, even called "a big challenge", and that "the first big challenge", including the three major difficulties test: overheating, high testing cost and lack for 3D package characteristics optimization test tools or EDA software. According to the three major difficulties of 3D integrated circuit testing silicon vias connected based on the proposed four corresponding The optimization strategy, the main contents and innovations are as follows:? According to the test of overheating and high test cost of these two difficulties, this paper presents a test strategy based on thermal drive. This strategy includes a scan tree new test structure and test vector ordering algorithm. Three dimensional integrated circuit test based on scan tree structure, can effectively to reduce the test time of three-dimensional integrated circuits, test data compression, so as to optimize the cost of testing, after the combination of test vector ordering algorithm, can reduce the cost of testing at the same time, effectively reduce the circuit of regional hot temperature, solve the test problem. Aiming at the difficulty of overheating? High testing cost, proposed cost optimization strategy in 3D binding and binding integrated circuit based testing. Unlike previous test cost model, we not only consider the testing time, also consider the number of vias in silicon test assembly The effect of the optimization strategy. By changing the stacking sequence of the three-dimensional integrated circuit, and the optimization of TAM (test access mechanism) bandwidth allocation, to minimize the cost of test. The same? Aiming at the difficulty of high testing cost, this paper from the three-dimensional integrated circuit testing point before binding, puts forward corresponding optimization strategy. The strategy of using nuclear segmentation technology, combined with an optimization algorithm, the cost of testing in the optimization of binding, has a very good effect.? for the lack of 3D optimization test tools or EDA software and test the high cost of these two difficulties, this paper introduces the advanced tools of double speed tester, and puts forward the double TAM speed test optimization strategy on this, so we can introduce a testing tool for 3D package characteristics optimization, and reduce the cost of test circuit, achieve the double-edged sword effect.

【学位授予单位】：清华大学
【学位级别】：博士
【学位授予年份】：2015
【分类号】：TN407

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