50Mbps低功耗时钟数据恢复电路设计

发布时间：2018-01-16 20:30

本文关键词：50Mbps低功耗时钟数据恢复电路设计　出处：《哈尔滨工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：串行传输技术仅采用数据线,节省了传输成本,降低了共享时钟引起噪声,是当今信息传输的主要方式。时钟数据恢复电路(CDR)是串行传输系统接收端的核心,其主要功能是提取嵌入到数据流中的时钟信息,在该时钟信号的帮助下进行采样,恢复传输的数据,以消除数据在发送器、接收器间传输引入的抖动。对于目前已经量产化的单芯片以太网物理层收发器,百兆内的传输速率以及灵活的电源管理架构,在保证传输速率的要求下,低功耗时钟数据恢复是基本诉求。本文使用SMIC0.18μm CMOS工艺实现50Mbps低功耗时钟数据恢复电路的设计,采用基于锁相环带外部参考时钟的全速率双环结构。为了提高稳定性,环路选择三阶;为了实现低功耗,压控振荡器(VCO)采用单端五级环形结构;同时滤波器电容使用MOS管电容以节省版图面积。使用Verilog-A并利用移位寄存器结合异或来实现输入随机NRZ序列的产生,以便对CDR进行测试。CDR环路在74.6us完成锁定,恢复的数据能够正确跟随输入,且恢复的时钟下降沿在输入数据中间采样,控制线上的纹波为1.54m V,系统恢复的时钟上升沿峰值抖动为183ps,恢复的数据峰值抖动为189.6ps。版图布局与绘制时提前考虑衬底噪声的影响,通过各方面的权衡以弥补电路设计中的不足,主要措施如:提高匹配性、物理距离隔离以及保护环等。后仿环路锁定时间为77.04us,控制线上抖动小于1m V,时钟的峰峰值抖动约为44ps。同时,随着芯片集成度的提高,衬底噪声已成为混合信号电路设计的难题。数字电路向衬底注入噪声,并经过衬底传播损害敏感模拟电路性能,使得系统可靠性降低甚至失效。为了具体分析衬底噪声对CDR性能的影响,通过衬底噪声的耦合原理,建立了CDR衬底等效模型、噪声源模型、N_well模型和电源/地线模型。将建立的模型应用于CDR电路中,由仿真知衬底噪声使压控振荡器的输出频率受到影响,系统锁定时间延长,恢复的时钟和数据峰值抖动增加,环路稳定性下降。为了有效地抑制衬底噪声,在建立的CDR衬底模型中加入保护环,测得环路锁定时间由噪声影响的80.82us缩减至74.3us,恢复的时钟抖动和数据抖动明显减小。
[Abstract]:The serial transmission technology only uses the data line, which saves the transmission cost and reduces the noise caused by the shared clock. Clock data recovery circuit (CDR) is the core of serial transmission system, and its main function is to extract the clock information embedded in the data stream. With the help of the clock signal, the transmitted data is sampled to recover the transmitted data to eliminate the jitter caused by the data transmission between the transmitter and the receiver.; for the single chip Ethernet physical layer transceiver which has been mass-produced at present. Within 100 megabytes of transmission rate and flexible power management structure, under the requirements of ensuring the transmission rate. Low power clock data recovery is the basic demand. In this paper, 50 Mbps low power clock data recovery circuit is designed using SMIC0.18 渭 m CMOS technology. A full rate double loop structure based on PLL with external reference clock is adopted. In order to improve the stability, the loop selects the third order. In order to achieve low power consumption, the VCO (Voltage controlled oscillator) adopts a single-ended five-stage ring structure. At the same time, the filter capacitor uses the MOS transistor capacitor to save the layout area, and uses the Verilog-A and the shift register to combine the XOR to realize the generation of the input random NRZ sequence. In order to test the CDR, the CDR loop is locked at 74.6us, the recovered data can follow the input correctly, and the recovered clock drop edge is sampled in the middle of the input data. The ripple on the control line is 1.54 MV, and the peak jitter of the rising edge of the system recovery clock is 183ps. The peak jitter of recovered data is 189.6 ps.The influence of substrate noise is considered ahead of time when layout layout and drawing are taken into account. The main measures such as improving matching ability can compensate for the deficiency in circuit design through various tradeoffs. Physical distance isolation and protection ring, etc. The locking time of the back loop is 77.04us. the jitter on the control line is less than 1m V, and the peak jitter of the clock is about 44ps. at the same time. With the improvement of chip integration, substrate noise has become a difficult problem in the design of mixed signal circuits. Digital circuits inject noise into the substrate and propagate through the substrate to damage the performance of sensitive analog circuits. In order to analyze the influence of substrate noise on CDR performance, the equivalent model and noise source model of CDR substrate are established by the coupling principle of substrate noise. The output frequency of the VCO is affected by the substrate noise and the locking time of the system is prolonged. The peak jitter of recovered clock and data increases and the loop stability decreases. In order to suppress the substrate noise effectively, the protection ring is added to the established CDR substrate model. The loop locking time was reduced from 80.82us to 74.3us. the recovered clock jitter and data jitter were reduced obviously.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN432

【参考文献】