12位低噪声双极性DAC电路设计及物理实现

发布时间：2018-01-22 10:52

本文关键词： 数模转换器 dual-ladder电阻分压型结构自调整双极性电压源噪声甲乙输出级　出处：《湘潭大学》2015年硕士论文　论文类型：学位论文

【摘要】：数模转换器(digital-to-analog convertor,DAC)是连接在模拟IC与数字IC间的重要接口之一,是很多SOC芯片中不可或缺的一部分,本文设计的数模转换器(DAC)是用于MEMS加速度计中,它是为了给系统提供一个稳定的偏压从而消除重力加速度对加速度计的影响,本课题是属于国家十二五重大专项,MEMS检波器与地震数据采集系统关键技术的子项目。系统对DAC的要求包括:分辨率为12bit,电源电压为±5V,差分参考电压为+3.7V和-3.7V,微分非线性误差(Differential non-linearity,DNL)小于0.25LSB,积分非线性误差(Integral nonlinearity,INL)小于2LSB,且要求DAC的噪声小于-120dBV?√。所设计的DAC采用的是dual-ladder电阻分压型结构,其结构特点为高6位粗分压电阻阵列和低6位细分压电阻阵列,这样相比于普通的电阻串分压型结构,可降低电阻匹配难度和版图布局的难度。为避免传统电压源结构所产生的电压对称性差和不精准的问题,提出了自调整双极性电压源的结构来产生3.7V和-3.7V的参考电压,并且自调整电压源中的反馈电阻即利用的电阻分压阵列中的电阻,有效的减小了芯片面积。由于系统加速度计低噪声的要求,详细分析了DAC的输出噪声来源,并且从INL、噪声以及功耗等方面进行折中考虑,选取合适的DAC电阻阵列单位电阻值,并进行两次流片对比对噪声进行优化。另外,由于DAC输出端需要接一个160Ω的电阻和一个330μF的大电容,为使得输出能在300ms内达到稳定,输出缓冲器采用甲乙输出级来减小输出的稳定时间。设计方法采用的是模拟集成电路设计的一般流程,根据指标要求完成各个工艺角下的前后仿真,进行了版图设计、流片、测试等工作。此DAC在旺宏(MIXC)0.5um CMOS工艺中得以流片实现,测试得到DAC的整体噪声在3Hz时为-120dBV?√,而在15Hz时接近-140dBV?√,结果满足系统指标的要求,并且此DAC被成功的应用到MEMS加速度计中。
[Abstract]:Digital-to-analog converter DAC is one of the important interfaces between analog IC and digital IC. It is an indispensable part of many SOC chips. The digital-to-analog converter designed in this paper is used in MEMS accelerometers. It is to provide a stable bias to the system so as to eliminate the impact of the acceleration of gravity on the accelerometer. MEMS geophone and seismic data acquisition system key technology subprojects. The system requirements for DAC include: resolution of 12 bits, power supply voltage of 卤5V. The differential reference voltage is 3.7V and -3.7V, and the differential nonlinear error is less than 0.25LSB. The integral nonlinear error is less than 2LSBand the noise of DAC is less than -120dBV? The DAC is designed with a dual-ladder resistor split voltage structure, which is characterized by a high 6 bit coarse partial voltage resistor array and a low 6 bit subdivided voltage resistance array. Compared with the common resistance series voltage divider structure, it can reduce the difficulty of resistor matching and layout. In order to avoid the problem of voltage symmetry and inaccuracy caused by the traditional voltage source structure. The structure of self-adjusting bipolar voltage source is proposed to generate 3.7V and -3.7V reference voltage, and the feedback resistance in the self-adjusting voltage source is the resistance in the resistor partial voltage array. Because of the low noise requirement of the accelerometer, the source of output noise of DAC is analyzed in detail, and the compromise is made from the aspects of INL, noise and power consumption. Select the appropriate unit resistance of DAC resistor array and optimize the noise by comparing the two flowsheets. Because the DAC output needs a resistor of 160 惟 and a large capacitance of 330 渭 F, the output can be stabilized within 300ms. The output buffer adopts A / B output stage to reduce the stable time of output. The design method adopts the general flow of analog integrated circuit design and completes the simulation of each process angle according to the requirements of the index. Layout design, flow sheet, test and so on are carried out. This DAC can be realized in the CMOS process. The global noise of DAC is -120dBV? And close to -140 dBV at 15 Hz? The results meet the requirements of the system, and the DAC is successfully applied to the MEMS accelerometer.
【学位授予单位】：湘潭大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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