适用于sigma_delta ADC的分辨率可配置数字抽取滤波器设计

发布时间：2018-01-23 18:54

本文关键词： 模数转换器分辨率可配置数字抽取滤波器 CIC滤波器低功耗　出处：《华中科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着集成芯片的广泛使用,超大规模集成电路也向着高速度、低功耗的方向快速发展。模数转换器是集成芯片中数据转换与传输的核心模块,ΣΔADC也在近年来模数转换器的研究设计及应用中异常突出。数字抽取滤波器是ΣΔADC的重要组成模块,基于此背景,本文设计了适用于ΣΔADC的分辨率可配置的数字抽取滤波器。ΣΔADC主要包括ΣΔ调制器和数字抽取滤波器两个模块,所以本论文先对ΣΔADC和调制器的理论基础进行了深入的分析研究。ΣΔADC的数据转换要经过过采样、噪声整形、抽取和滤波四个阶段,ΣΔ调制器完成过采样和噪声整形两个任务,并以此提高模数转换器的分辨率;数字抽取滤波器完成抽取和滤波。数字滤波器一般分为FIR滤波器和IIR滤波器两种,而常用的FIR滤波器有级联积分梳状滤波器、补偿滤波器和半带滤波器。级联积分梳状(CIC)滤波器是其中结构最简单的一种滤波器结构,被经常用于多级数字滤波器的第一级。而在工业用ΣΔADC中,由于对转换精度及滤波的要求不高,所以也通常只用CIC滤波器结构实现数字抽取滤波。本次设计采用的是单级的积分梳状滤波器结构,由于设计要求并行输出数据转换后的数字值,所以进行结构的变换,并在此基础上通过改变降采样率进行分辨率可配置,32~4096倍的降采样率分别对应5~12bit的分辨率。在论文设计部分分别对串行输出单级CIC滤波器和结构转换后的并行输出滤波器进行了功耗和面积的比较,综合设计要求,采用并行输出数字滤波器结构。论文采用SMIC 0.18μm 3.3V Mix Signal 1P5M工艺对分辨率可配置数字抽取滤波器进行仿真验证。ΣΔ调制器输出有效分辨率达到11.66bit,数字抽取滤波器输出有效分辨率达到11.55bit,由于最高位为符号位,所以满足设计要求。同时分辨率可配置电路实现了低功耗设计。
[Abstract]:With the wide use of integrated chips, VLSI is also developing rapidly in the direction of high speed and low power consumption. Analog-to-digital converter (ADC) is the core module of data conversion and transmission in integrated chips. 危螖 ADC is also prominent in the research, design and application of ADC in recent years. Digital decimation filter is an important module of 危螖 ADC, based on this background. A digital decimation filter with configurable resolution for 危螖 ADC is designed in this paper. 危螖 ADC consists of two modules: 危螖 modulator and digital decimation filter. In this paper, the theoretical basis of 危螖 ADC and modulator is analyzed. The data conversion of 危螖 ADC is oversampled, noise shaping, decimated and filtered. The 危螖 modulator accomplishes the tasks of oversampling and noise shaping, and improves the resolution of the ADC. Digital decimation filter completes decimation and filtering. Digital filter is generally divided into two types: FIR filter and IIR filter, while the commonly used FIR filter has cascaded integral comb filter. The cascade integral comb filter is one of the simplest filter structures. It is often used in the first stage of multistage digital filters. In industrial 危螖 ADC, the conversion accuracy and filtering requirements are not high. So we usually only use the CIC filter structure to realize digital decimation filter. This design uses a single-stage integrated comb filter structure, because of the design requirements of the parallel output data converted digital value. Therefore, the structure of the transformation, and on this basis by changing the sampling rate of the resolution can be configured. In the design part of the thesis, the single-stage CIC filter with serial output and the parallel output filter after structure conversion are used to consume power respectively. And the area. Comprehensive design requirements. Parallel output digital filter structure is adopted. SMIC 0.18 渭 m 3.3V Mix Signal is used in this paper. 1P5M process is used to verify the resolution configurable digital decimation filter. The effective resolution of 危螖 modulator output is 11.66 bit. The output effective resolution of the digital decimation filter is 11.55 bit. because the highest bit is the symbol bit, it meets the design requirements. At the same time, the resolution configurable circuit realizes the design of low power consumption.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN713

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