SRAM电路抗工艺变化的关键技术研究

发布时间：2018-01-24 14:29

本文关键词： SRAM 工艺变化低电压复制位线灵敏放大器时序偏差失调电压　出处：《安徽大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着集成电路(IC)行业快速发展,高集成度,高速低功耗已成为未来集成电路发展的趋势。高集成度需要更小的半导体工艺尺寸,然而工艺尺寸较小会引起较大的工艺偏差。为了实现低功耗的目的,供电电压也在不断降低。然而电源电压不断降低加重了工艺偏差对电路的影响。SRAM作为IC中重要的组成部分,这种不断增大的工艺偏差会对SRAM性能造成严重的影响,尤其对SRAM的工作速度,功耗以及稳定性方面影响最为突出。针对这些工艺偏差带来的问题,本文从复制位线以及灵敏放大器的的角度做了一些抗工艺变化的改进。本文主要做的研究工作如下:首先分析了 SRAM基本框架结构以及工作原理,然后分析了工艺偏差对SRAM里面时序信号以及灵敏放大器的影响,基于对两者的分析,对已有的几种常见的时序控制电路以及灵敏放大器做出分析,并且在SIMC 28nm工艺下对其结果进行仿真和比较。针对工艺变化给SRAM电路带来的负面影响,本文从复制位以及灵敏放大器两个方面做了改进,首先提出了一种带有触发器的流水型复制位线技术用于减少工艺变化对时序信号的影响,然后又从灵敏放大器的角度提出了一种自反馈衬底调节的抗工艺变化的灵敏放大器电路用于减少工艺偏差对灵敏放大器失调电压的影响。为了验证所提的改进型电路的性能,我们对所提电路进行蒙特卡洛仿真,与传统的复制位线技术仿真结果相比,带有触发器的流水型复制位线技术抗工艺偏差减少了 81.34%。与传统统的电压型灵敏放大器仿真结果相比,带有自反馈衬底调节的抗工艺变化的灵敏放大器的失调电压减少了 31.73%。
[Abstract]:With the rapid development of IC industry, high integration, high speed and low power consumption have become the trend of IC development in the future. However, the smaller size of the process will cause a large process deviation, in order to achieve the purpose of low power consumption. The power supply voltage is also decreasing. However, the decrease of the supply voltage increases the influence of the process deviation on the circuit. SRAM is an important part of IC. This increasing process deviation will have a serious impact on the performance of SRAM, especially on the operating speed, power consumption and stability of SRAM. In this paper, some improvements are made from the point of view of replicating bit lines and sensitive amplifiers. The main research work of this paper is as follows: firstly, the basic frame structure and working principle of SRAM are analyzed. Then, the influence of process deviation on the timing signal and sensitive amplifier in SRAM is analyzed. Based on the analysis of both, several common timing control circuits and sensitive amplifiers are analyzed. The results are simulated and compared under the SIMC 28nm process. In view of the negative effects of the process changes on the SRAM circuits, this paper improves on the replication bit and the sensitive amplifier. Firstly, a income type replica bit line technique with trigger is proposed to reduce the influence of process change on timing signal. Then, from the point of view of sensitive amplifier, a kind of self-feedback substrate adjusted sensitive amplifier circuit is proposed to reduce the effect of process deviation on offset voltage of sensitive amplifier. Circuit performance. We do Monte Carlo simulation of the circuit and compare the simulation results with the traditional replica bit line technology. The income type replica bit line with flip-flop reduces the process deviation by 81.34. Compared with the simulation results of the traditional voltage-mode sensitive amplifier. The offset voltage of the sensitive amplifier with self-feedback substrate adjustment is reduced by 31. 73.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP333;TN722

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