一种低功耗的双积分型模数转换器的设计

发布时间：2018-01-24 21:26

  本文关键词： 迟滞比较器 双积分型模数转换器 自动调零电路 积分器　出处：《辽宁大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着集成电路在微电子领域的迅猛发展,现实中数字计算和数字处理电路的应用变得更加广泛,无论是在高新仪器的设计、无线电通讯领域、各种成像电路系统中,模数转换器(Analog to digital converter:ADC)是其中重要的组成部分,而且其性能的优劣会对所设计的电路产生最直接的影响。所以,我们针对在实际中应用的不同来选择需要的ADC。首先,介绍了模数转换器在现代电子技术中的发展现状、地位、作用以及它的发展前景。其次,本文针对压力测量和承重等仪器对模数转换器的需要,对比几种模数转换在性能和成本上的差异,本文选择的是具有高精度、低速、低功耗的双积分型ADC。再次,介绍了模数转换器的工作原理,和其不同类型的电路结构和性能差异。最后,对双积分型模数转换器电路进行设计和仿真,并得到最终的设计参数。而要想研究双积分型ADC,那么就需要先了解其工作原理,分析对比其系统结构的特点与非理想特性。本文在研究过程中,将双积分型ADC划为几个重要的子模块:即采样保持电路、积分器、比较器、计数器、带隙基准源等各部分,并且在每一部分的电路设计后进行仿真,查看设计得到的电路是否符合设计要求的指标。然后,对设计的电路进行整体仿真,查看与理想转换器之间产生的误差,并找出产生误差的原因。本论文在双积分型ADC电路研究设计有以下几个特点:一是在积分器设计中引入了自动调零电路,可以有效的抵消在生产工艺中引起的失调现象;二是在比较器电路的设计上采用了迟滞比较器,降低电路噪声对比较器输出的影响;三是通过电路设计的优化,本文设计的双积分型模数转换器电路的功耗很低。本文设计的双积分型ADC指标参照芯片ICL7109为:精度为12 bit,采样率为9K,输入电压范围为0~5 V,功耗为10 m W。而本文在基于Chrt 35.0um标准CMOS工艺下进行电路设计,通过仿真得到ADC的SNR为70.98,有效位数为11.5 bit,采样率为10K,输入电压范围为0~5 V,功耗为1.12 m W,符合设计要求。
[Abstract]:With the rapid development of integrated circuits in the field of microelectronics, the application of digital computing and digital processing circuits has become more and more extensive in the field of the design of high-tech instruments and radio communication. Analog to digital convertor: ac is an important part of various imaging circuit systems. And its performance will have the most direct impact on the design of the circuit. Therefore, we choose the need for ADCs according to the different applications in practice. First of all. This paper introduces the current situation, status, function and development prospect of A / D converter in modern electronic technology. Secondly, this paper aims at the need of A / D converter for pressure measurement and load-bearing instruments. Compared with the differences in performance and cost of several analog-to-digital converters, this paper chooses dual-integral ADCs with high precision, low speed and low power consumption. Thirdly, the working principle of ADC is introduced. And its different types of circuit structure and performance differences. Finally, the design and simulation of the dual integral ADC circuit, and get the final design parameters. Then it is necessary to understand its working principle and analyze and compare the characteristics of its system structure and its non-ideal characteristics. In the course of the research, the dual-integral ADC is divided into several important sub-modules: sample-and-hold circuit. Integrator, comparator, counter, bandgap reference source and other parts, and in each part of the circuit design simulation, to see whether the designed circuit meets the design requirements. Then. The designed circuit is simulated as a whole to see the error between the designed circuit and the ideal converter. And find out the cause of the error. This paper has the following characteristics in the research and design of dual-integral ADC circuit: first, the integration of the introduction of automatic zero adjustment circuit. Can effectively counteract the phenomenon of imbalance in the production process; Second, the hysteresis comparator is used in the design of comparator circuit to reduce the effect of circuit noise on the output of comparator. The third is the optimization of circuit design. The power consumption of the dual integral ADC circuit designed in this paper is very low. The dual integral ADC index reference chip ICL7109 is: the precision is 12 bits and the sampling rate is 9K. The input voltage range is 0 ~ 5 V and the power consumption is 10 MW. The circuit is designed based on Chrt 35.0um standard CMOS process. The simulation results show that the SNR of ADC is 70.98, the effective bit is 11.5 bits, the sampling rate is 10K, the input voltage range is 0 ~ 5 V, and the power consumption is 1.12 MW. Meet the design requirements.
【学位授予单位】：辽宁大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
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本文编号：1461061