复杂电路功耗自测试方法研究与仿真

发布时间：2018-02-01 00:17

本文关键词： 无关位填充低功耗内建自测试电路　出处：《计算机仿真》2017年08期 　论文类型：期刊论文

【摘要】：对电路分布路径低功耗内建自测试,在电路故障检测方面具有重要意义。电路功耗内建自测时,需对电路构造距离序列进行寻优,传统方法主要通过对电路的X位做低功耗填充,无法对电路构造距离序列进行寻优,导致故障测试结果不准确。提出无关位填充的电路低功耗内建自测试方法。将测试向量与扫描链中响应数据分块相容,待测电路的功耗划分为动态功耗和静态功耗,依据划分结果获取电路节点的动态功耗,计算出连续输入测试矢量序列的电路功耗,得到电路的平均功耗和峰值功耗,获取待测电路时序逻辑之间的数据传递关系,融合于改进细胞自动机构造预确定距离序列,利用遗传理论对该距离序列进行寻优,得到最佳预确定测试序列,完成电路低功耗内建自测试,达到电路故障检测的目的。仿真结果表明,所提方法检测电路故障精确度高。
[Abstract]:Low-power built-in self-test of circuit distribution path is of great significance in circuit fault detection. When the circuit power built-in self-test, it is necessary to optimize the circuit construction distance sequence. The traditional method can not optimize the circuit construction distance sequence by filling the X bit of the circuit with low power consumption. The fault test results are inaccurate. A low power built-in self-test method with independent bit filling is proposed. The test vector is compatible with the response data partitioned in the scan chain. The power consumption of the circuit under test is divided into dynamic power consumption and static power consumption. According to the partition results, the dynamic power consumption of the circuit node is obtained, and the circuit power consumption of the continuous input test vector sequence is calculated. The average power consumption and peak power consumption of the circuit are obtained, and the data transfer relationship between sequential logic of the circuit under test is obtained, which is fused to the improved cellular automata to construct the pre-determined distance sequence. Genetic theory is used to optimize the distance sequence to obtain the best pre-determined test sequence. The low power consumption built-in self-test of the circuit is completed and the purpose of circuit fault detection is achieved. The simulation results show that. The proposed method has high accuracy in detecting circuit faults.
【作者单位】：青海民族大学计算机学院;
【分类号】：TN407
【正文快照】： 1引言目前,随着电子技能化技术的不断提升,集成电路系统复杂度和其工艺复杂度也在逐渐的增加,促使了集成电路测试面临着很多的挑战[1-3]。在实际的集成电路测试中,电路测试数据量增长迅速,需要消耗大量的测试时功耗,降低了电路的可靠性[4-6]。低功耗内建自测试方法可以构造预

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