多FPGA验证平台的SoC逻辑划分方法及应用

发布时间：2018-02-07 17:57

本文关键词： 多FPGA SoC 芯片验证逻辑划分　出处：《大连理工大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着SoC和IP核技术的推广,逻辑验证已成为芯片设计领域的一个主要难题。许多案例中,芯片的逻辑验证团队规模甚至超过逻辑设计团队。软件仿真技术作为目前最常见的逻辑验证方法,其灵活性值得肯定,但具有验证规模小、效率低等致命缺陷。FPGA硬件验证技术可提供优良的验证准确性和高效性,多FPGA验证技术可实现对大规模芯片的逻辑验证。本论文致力于运用多PFGA验证平台搭建芯片设计的原型系统,以实现大规模SoC芯片的逻辑验证。通过叙述SoC和IP核复用技术为芯片验证带来规模上挑战和机遇,展开了芯片验证方法的叙述,讨论软硬件方法存在的问题。我们重点介绍了FPGA的验证方法,并致力于解决多PFGA原型验证系统中存在的两大关键问题：SoC逻辑划分和多FPGA芯片互连。本文经过逻辑模块树提取和资源需求分析后,设计了逻辑划分算法,算法的时间复杂度为O(n)。逻辑划分算法实现中,运用现有EDA软件进行资源信息提取,以XML文件进行逻辑模块树的记录,最终依据算法结果指导RTL代码修改。多FPGA互连问题则PCIe,总线架构,以RocketIO进行实现。为确保算法设计有效,本文在自研的多FPGA原型验证平台上,使用RSA硬件加密算法核和Leon3 SoC IP核进行了正确性、高效性、统计实验。实验结果表明：多FPGA验证平台设计合理；SoC逻辑划分算法正确且高效；多FPGA互连结构可扩展。论文工作有一定的创新性和应用价值。
[Abstract]:With the spread of SoC and IP technologies, logic verification has become a major challenge in the field of chip design. The size of the logical verification team is even larger than that of the logical design team. As the most common logic verification method at present, the flexibility of the software simulation technology is commendable, but it has a small scale of verification. Low efficiency and other fatal defects. FPGA hardware verification technology can provide excellent verification accuracy and efficiency, Multiple FPGA verification technology can realize the logical verification of large scale chips. This thesis is devoted to building a prototype system of chip design using multiple PFGA verification platform. In order to realize the logical verification of large scale SoC chip, the paper describes the challenges and opportunities brought by SoC and IP core reuse technology to the scale of chip verification, and presents the method of chip verification. The problems of software and hardware methods are discussed. We mainly introduce the verification method of FPGA. And it is devoted to solve the two key problems in the prototype verification system:: SoC logic partition and multi-#en1# chip interconnection. After the logic module tree extraction and resource requirement analysis, the logic partition algorithm is designed in this paper. In the realization of logic partition algorithm, the existing EDA software is used to extract the resource information, and the XML file is used to record the logic module tree. Finally, according to the result of the algorithm, the RTL code is modified. In order to ensure the effective design of the algorithm, the multi-#en1# interconnection problem is implemented on the multi-#en3# prototype verification platform, which is based on the bus architecture and implemented by RocketIO. The RSA hardware encryption algorithm core and the Leon3 SoC IP core are used to carry out the correctness, high efficiency and statistical experiment. The experimental results show that the multi-#en3# verification platform is designed reasonably and the algorithm is correct and efficient. Multi-FPGA interconnection structure is extensible. The work of this paper has some innovation and application value.
【学位授予单位】：大连理工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

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