GLSI多层铜布线阻挡层CMP及其后清洗表面粗糙度的研究

发布时间：2018-02-24 18:26

本文关键词： 集成电路化学机械抛光阻挡层抛光液清洗液表面粗糙度　出处：《河北工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着集成电路技术的迅猛发展和进步,芯片的集成度越来越高,特征尺寸逐渐减小,线宽也越来越窄,对集成电路性能的要求越来越高,如提高集成度、解决互连延迟,还要满足性能、频宽和功耗的要求等。目前,国际上特征尺寸为22nm/20nm的极大规模集成电路(GLSI)已实现大规模生产,晶圆尺寸为300mm,多层金属互连层数高达10层以上,为了保证最终晶圆各种参数乃至器件性能满足客户的要求,就要求在每一层布线之后,都能够得到较高的晶圆表面平整度。化学机械抛光(CMP)是目前公认的能够有效实现全局平坦化的技术,而在集成电路制造过程所需要的CMP中,阻挡层的CMP是最终决定晶圆平坦化效果的关键环节,直接影响器件性能和成品率。阻挡层的CMP过程涉及到对铜、钽、介质这三种不同性质材料同时进行抛光,最终将钽和介质完全去除,剩余铜线条,由于铜质地较软,抛光后表面易产生微划伤、腐蚀坑等问题,这都对阻挡层的CMP提出了更大的挑战,并且抛光后表面会有颗粒的粘附,这些问题都影响晶圆表面粗糙度。因此对阻挡层CMP过程以及清洗液进行深层次研究就有了非常重要的实践意义。本文主要通过单因素实验探索抛光工艺参数、抛光液组分及清洗液成分对铜表面粗糙度的影响,对实验数据进行整理,对所得结果进行研究分析,并将研究的最后成果运用到300mm铜布线晶圆阻挡层平坦化实验中。抛光后对实验晶圆片进行表面缺陷的检测,测试结果为抛光后单层铜布线碟形坑低于450?,蚀坑低于200?,铜膜表面粗糙度为0.679nm,各项检测结果均满足工业生产要求。实验结果表明此弱碱性阻挡层抛光液实现阻挡层平坦化的可行性,并且其组分简单,环保,易清洗,其中不含传统增膜腐蚀抑制剂BTA,不含不稳定的氧化剂成分,不存在酸性抛光液导致的腐蚀、成分复杂,成本高等问题。通过阻挡层CMP后清洗液的清洗,抛光片表面微缺陷密度与表面微粗糙度进一步降低,获得了良好的表面形貌。
[Abstract]:With the rapid development and progress of the integrated circuit technology, the integration degree of the chip becomes higher and higher, the characteristic size decreases gradually, the line width becomes narrower and narrower, and the performance of the integrated circuit is required more and more, such as improving the integration level and solving the interconnect delay. It also needs to meet the requirements of performance, bandwidth and power consumption. At present, the international maximum scale integrated circuit (GLSI) with a characteristic size of 22nm / 20nm has been produced on a large scale, with a wafer size of 300mm and a multilayer metal interconnect layer of more than 10 layers. In order to ensure that the final wafer parameters and even device performance meet customer requirements, after each layer of wiring, Chemical mechanical polishing (CMP) is currently recognized as a technology that can effectively achieve global flatness, while in CMP, which is required for integrated circuit manufacturing, The CMP of the barrier layer is the key to determine the effect of wafer flattening, which directly affects the performance and the yield of the device. The CMP process of the barrier layer involves the simultaneous polishing of copper, tantalum and dielectric materials with different properties, such as copper, tantalum and dielectric. Finally, tantalum and media are removed completely, and the remaining copper wire strips are removed completely. Due to the softer quality of copper, the surface of polished copper is prone to be scratched, corrosion pits and so on. This poses a greater challenge to the CMP of the barrier layer, and there will be particle adhesion on the polished surface. All of these problems affect the surface roughness of wafer. Therefore, it is very important to study the CMP process of barrier layer and the cleaning liquid deeply. In this paper, single factor experiments are used to explore the polishing process parameters. The effects of the components of polishing liquid and cleaning liquid on the surface roughness of copper were analyzed. The final results of the study were applied to the experiment of flattening the barrier layer of 300mm copper wiring wafer. After polishing, the surface defects of the wafer were detected, and the results showed that the surface defect of the wafer was less than 450? , etch pit less than 200? The surface roughness of copper film is 0.679 nm, and all the test results meet the requirements of industrial production. The experimental results show that it is feasible to flatten the barrier layer by using this weakly alkaline barrier layer polishing liquid, and its composition is simple, environmental protection is easy, and it is easy to clean. There are no traditional corrosion inhibitor, no unstable oxidant, no corrosion caused by acid polishing liquid, complex composition, high cost and so on. The surface microdefect density and the surface microroughness of the polishing wafer were further reduced and the good surface morphology was obtained.
【学位授予单位】：河北工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN405

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