新型凹槽栅极应变Ge NMOS器件设计与特性研究

发布时间：2018-03-02 13:52

本文选题：应变Ge　切入点：NMOS　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着微电子技术的发展,晶体管的特征尺寸越来越小,集成电路的规模也越来越大,采用传统的等比例缩小原则提升集成电路性能的方法越来越受到物理与工艺的限制,制约了集成电路性能的进一步发展。应变Ge材料与技术具有载流子迁移率高、能带可调且与成熟的硅工艺兼容的优势,成为了延续摩尔定律进一步发展的有效途径。本文重点研究了应变Ge材料载流子有效质量、散射几率和迁移率等关键物理参数随应力强度、晶面的变化规律,以及应变Ge材料性能增强机制,分析比较了应变Ge MOS器件沟道应力引入机制,提出了适于集成电路工艺的沟道应力引入方法;研究了应变Ge MOS的界面特性,分析了界面态生成的机制和栅漏电机制,优化了栅介质的结构,获得了优化的栅结构及其制备方法;在以上研究的基础上,本文提出采用多数载流子形成导电沟道的新型应变Ge NMOS结构,有效地解决了掺杂元素硼(B)在Ge中激活率和p型Ge载流子迁移率低的问题;为了获得更高的器件电流开关比,进一步地提出了基于GOI的凹槽栅极应变Ge NMOS结构,该结构非常易于集成;通过仿真软件,研究了沟道长度、栅极凹槽角度和深度等几何结构参数对该器件阈值电压、开态电流、开关比等电学特性的影响;定量地分析了沟道掺杂、栅极介电常数等物理参数对器件电学特性的影响,揭示了电学特性随几何结构、物理参数参数的演化规律,获得了优化的器件结构、物理参数;给出了优化的凹槽栅极应变Ge NMOS器件工艺实现方法,并进行了模拟仿真,结果表明,栅极氧化层应选用高介电常数的high-K材料,且从开关比的角度考虑厚度为5nm最为合适;栅极金属功函数应尽量的大以获得更大的器件开关比;栅极凹槽角度较小时,器件关态电流IOFF会较大,从而降低器件的开关比;最后,提出了应用于集成电路的栅极凹槽应变Ge CMOS,形成了反向器单元,仿真结果表明,在输入输出摆幅为2V时,高噪声容限为0.933V,低噪声容限为0.973V。为高性能应变Ge的集成电路的发展提供了理论支撑。
[Abstract]:With the development of microelectronic technology, the characteristic size of transistors becomes smaller and smaller, and the scale of integrated circuits becomes larger and larger. Strain GE materials and technologies have the advantages of high carrier mobility, tunable band and compatible with mature silicon processes. In this paper, the key physical parameters, such as effective mass of carrier, scattering probability and mobility of strained GE materials, are studied with stress intensity and crystal plane. The mechanism of strain GE material performance enhancement is analyzed and compared, the channel stress introduction method suitable for integrated circuit process is proposed, the interface characteristics of strain GE MOS are studied, the mechanism of channel stress introduction in strain GE MOS device is analyzed and compared, and the channel stress introduction method suitable for integrated circuit process is proposed. The mechanism of interface state generation and gate leakage are analyzed, the structure of gate dielectric is optimized, and the optimized gate structure and its preparation method are obtained. In this paper, a new strain GE NMOS structure with conducting channels formed by majority carriers is proposed, which can effectively solve the problem of low activation rate and p type GE carrier mobility in GE doped with boron B, in order to obtain a higher current-switching ratio. Furthermore, a grooved gate strain GE NMOS structure based on GOI is proposed, which is very easy to integrate, and the threshold voltage and open current of the device are studied by the simulation software, such as channel length, gate groove angle and depth, etc. The influence of the physical parameters such as channel doping, gate dielectric constant and other physical parameters on the electrical properties of the device is analyzed quantitatively, and the evolution law of the electrical characteristics with the geometric structure and the physical parameters is revealed. The optimized device structure and physical parameters are obtained, and the method of realizing the optimized gate strain GE NMOS device process is given, and the simulation results show that the gate oxide layer should be made of high-K material with high dielectric constant. Considering the thickness of 5 nm from the angle of switching ratio, the gate metal work function should be as large as possible in order to obtain a larger switch ratio, and when the angle of gate groove is small, the switching current IOFF of the device will be larger, thus reducing the switching ratio of the device. Finally, the grid grooves strain GE CMOSs used in integrated circuits are proposed, and the inverters are formed. The simulation results show that, when the input and output swing is 2V, The high noise tolerance is 0.933 V and the low noise tolerance is 0.973V. it provides theoretical support for the development of high performance strained GE integrated circuits.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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