集成电路容软错误加固锁存器方案研究与设计

发布时间：2018-03-04 04:23

本文选题：软错误　切入点：加固锁存器　出处：《合肥工业大学》2017年硕士论文　论文类型：学位论文

【摘要】：在集成电路制造水平不断发展的当下,芯片的集成度越来越高,工作频率越来越快,工作电压和晶体管的阈值电压不断降低,晶体管尺寸也在逐年减小,所以芯片电路内部节点临界电荷量也在持续的减少,导致电路软错误率不断上升。由于目前软错误对于集成电路影响日益加剧,针对已有的锁存器电路结构方案所存在的缺陷,设计了一个新的高速低功耗的加固锁存器结构。其中提出了一个新的C单元连接方法,大大降低了锁存模块的短路功耗;对输出级C单元进行改进,其自身内部节点的临界电荷量得到加强,并且稳固了输出节点的值,使其在输入端受到攻击时不会处于高阻状态,从而提升了锁存器整体的抗软错误能力。通过HSPICE在22nm预测模型下进行仿真,验证了该结构的可靠性,并与已有的一些优秀的抗软错误锁存器结构进行对比。实验结果显示了本文设计的锁存器牺牲了 25.78%的晶体管数目,来换取功耗、延迟、以及抗软错误性能方面的提升;功耗、延迟分别平均降低43.12%、46.25%,功耗延迟积降低了 37.61%～97.50%,平均值达到68.98%,可以说本设计在具有很高的可靠性的同时,功耗、延迟等指标也有大幅提升。
[Abstract]:At present, with the development of IC manufacturing level, the integration of chips is getting higher and higher, the working frequency is faster and faster, the operating voltage and the threshold voltage of transistors are decreasing, and the size of transistors is decreasing year by year. Therefore, the critical charge of the internal nodes of the chip circuit is also decreasing, which leads to the increasing soft error rate of the circuit. Because of the increasing influence of the soft error on the integrated circuit at present, the defects of the existing latch circuit structure are pointed out. A new high speed and low power reinforced latch structure is designed, in which a new C unit connection method is proposed, which greatly reduces the short circuit power consumption of the latch module, and improves the output level C unit. The critical charge of its own internal node is strengthened and the output node is stabilized so that it will not be in a high resistance state when the input is attacked. Thus, the overall anti-soft error capability of the latch is improved. The reliability of the structure is verified by HSPICE simulation under the 22nm prediction model. The experimental results show that the designed latch has sacrificed 25.78% transistors in exchange for power consumption, delay, and anti-soft error performance. The average delay is reduced by 43.12and 46.25, the power delay product is reduced by 37.61 and 97.50, the average value is up to 68.98. It can be said that the design has high reliability, and the power consumption, delay and other indexes are also greatly improved.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN40

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