基于BIST方法的新型FPGA芯片CLB功能测试方法

发布时间：2018-03-04 22:29

本文选题：现场可编程门阵列　切入点：可编程逻辑块　出处：《复旦学报(自然科学版)》2017年04期 　论文类型：期刊论文

【摘要】：新型FPGA普遍使用了6输入查找表以实现可编程逻辑,如Xilinx公司的Virtex 5系列、Ultrascale系列等.由于I/O数量有限,针对这些芯片的CLB功能测试,可选择ILA级联测试法并利用位流回读进行故障定位,但由于CLB存在路径互斥,覆盖所有故障所需配置较多,而位流回读较为缓慢,限制了定位速度.BIST测试法通过直接检测CLB的输出来发现故障,所需配置数量少于ILA级联法,但需要将测试激励传递到所有BUT导致端口负载大,布线存在困难.本文提出了一种将ORA中闲置资源配置为锁存器链,以便传递测试激励的方法.该方法降低了端口负载.同时利用剩余的逻辑资源建立扫描链,大幅加快了故障定位速度.在Xilinx 7系列FPGA上的实验结果表明,与其他文献所用测试方案比较,测试所需配置次数由30次降低到26次,故障定位所需时间在2.4MHz时钟驱动下可达61.35ns.
[Abstract]:The new FPGA generally uses six input lookup tables to implement programmable logic, such as Xilinx's Virtex 5 series ultrasound cale series. Due to the limited number of I / O, the CLB function test for these chips, We can choose ILA cascade test method and use bit stream backreading for fault location. However, due to the existence of path exclusion in CLB, more configurations are required to cover all failures, and bit stream backreading is slow. The location-speed .BIST test method detects faults by directly detecting the output of the CLB. The number of configurations required is less than that of the ILA cascade method, but the need to pass test incentives to all BUT results in a heavy port load. This paper presents a method of configuring idle resources in ORA as latch chains in order to transfer test excitation. This method reduces port load and establishes scanning chain using remaining logical resources. The experimental results on Xilinx 7 series FPGA show that, compared with the test schemes used in other literatures, the configuration times of the tests are reduced from 30 times to 26 times, and the time required for fault location can reach 61.35 ns under the driving of 2.4 MHz clock.
【作者单位】：复旦大学专用集成电路与系统国家重点实验室;
【分类号】：TN407

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