基于SVA功能验证方法的中断延迟控制器和GPIO的验证研究

发布时间：2018-03-09 13:25

本文选题：功能验证　切入点：SVA　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着集成电路一直在向高性能、高集成度、低功耗的SoC方向发展,功能验证在设计开发过程中变得越来越复杂和越来越重要。传统的验证技术和方法在开发周期,验证效率以及验证平台的可观性、可控性和可复用性等方面的表现已经不能够满足当前的需求。伴随着电子设计自动化技术的快速发展,各种各样的新型的验证技术和方法就如何提高验证效率,缩短开发周期以及开发可移植的验证组件和环境等方面做了很多的探索,他们已经在诸多方面弥补了传统验证技术和方法的不足。本文基于断言验证方法,主要研究了System Verilog Assertion的功能验证技术在实际项目中的应用。根据SVA的语言与验证技术特点,分析阐述了其在验证环境开发和使用过程中的优势。针对中断延迟控制器,提出了一个单靠形式化方法的功能验证设计方案,根据其功能规范的要求,使用SVA编写了用于断言和假设的属性,通过Jasper形式验证技术,实现了验证平台的搭建以及完成了该模块的功能验证工作。该方法在保证验证质量的同时有效的缩短了开发周期,提高了验证效率。另外,基于当前流行的OVM验证方法学对通用输入输出控制模块提出了一种断言覆盖率驱动的验证设计方案,在OVM类库的基础上实现了用于待测设计的OVC组件,通过断言模块的功能检测和覆盖率分析搭建了一个完整的验证平台,实现了一个高层次化,高覆盖率,可复用性强的验证环境。本文研究开发的验证环境和平台成功的完成了待测设计的功能验证,并已经应用到实际的项目中。中断延迟控制器的形式化验证方法已经推广到其他相似功能模块的验证工作,通用输入输出控制模块的验证组件和断言模块很好的复用到其他的项目。研究结果和实践表明,基于SVA的验证技术和方法实现的形式验证环境的功能覆盖率达到100%,并且有效地节省了开发时间,缩短了的验证周期;实现的OVM验证平台具有很高的可复用性,并且其功能覆盖率达到100%,代码覆盖率达到97.9%。
[Abstract]:With the development of integrated circuits in the direction of high performance, high integration and low power consumption, functional verification has become more and more complex and important in the process of design and development. The performance of verification efficiency and the observability, controllability and reusability of the verification platform can no longer meet the current needs. With the rapid development of electronic design automation technology, Various new verification technologies and methods have done a lot of research on how to improve the efficiency of verification, shorten the development cycle and develop portable verification components and environments. They have made up for the shortcomings of traditional verification techniques and methods in many aspects. Based on the assertion verification method, this paper mainly studies the application of System Verilog Assertion function verification technology in actual projects. According to the characteristics of SVA language and verification technology, This paper analyzes and expounds its advantages in the process of developing and using the verification environment. For interrupt delay controller, a design scheme of function verification based on formal method is proposed, according to the requirements of its function specification. The attributes used for assertion and hypothesis are written with SVA, and the verification platform is built and the function verification work of the module is completed by means of Jasper formal verification technology. This method can effectively shorten the development period while guaranteeing the verification quality. In addition, based on the popular OVM verification methodology, an assertion coverage driven verification design scheme is proposed for the general input and output control module. Based on the OVM class library, a OVC component is implemented for the design to be tested. Through the function detection and coverage analysis of the assertion module, a complete verification platform is built, which realizes a high level and high coverage. The verification environment and platform developed in this paper have successfully completed the functional verification of the design to be tested. The formal verification method of interrupt delay controller has been extended to other similar functional modules. The verification components and assertion modules of the Universal I / O control module are well reused to other projects. The function coverage of formal verification environment based on SVA is 100, and the development time is saved and the verification cycle is shortened. The OVM verification platform has high reusability. And its function coverage rate reaches 100%, the code coverage rate reaches 97.9%.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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