基于Verilog HDL的SPI协议可复用IP软核的设计与验证

发布时间：2018-03-10 12:13

  本文选题：SOC　切入点：IP软核　出处：《兰州大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着集成电路技术的高速发展,SOC技术已经越来越多的得到关注和应用,尤其是片上总线技术和IP技术的出现使其逐渐成为IC设计的主流技术。但是目前SOC的发展也面临巨大挑战,主要是IP复用技术和IP互连技术,因此研究IP复用技术对于SOC发展具有重要意义。SPI是Motorola公司开发的一种同步、高速、全双工的通信总线,因其信号线少、结构简单等特点被越来越多的芯片集成为通信总线。基于此,本文设计了两种可复用、可配置的SPI协议IP软核,为SOC设计中的IP互连提供灵活的SPI接口,这完全满足SOC技术的发展要求和发展方向,对于业界和SPI的推广应用都具有极高的意义和实用价值。论文采用自顶向下的设计思路设计了两种可复用的SPI协议IP软核。其中基于微控制器的SPI协议IP软核的设计主要关注SPI主机功能,制定了设计目标,使其可与8个从机通信,同时能设置通信速率和选择传输模式,并将接收逻辑和发送逻辑分开,为发送和接收数据设计了双缓冲机制。根据设计目标划分了子模块并给出了完整的模块问互连框图,说明了寄存器设置,论述了关键子模块的Verilog HDL实现过程,包括设计思路分析,微控制器接口模块、时钟逻辑模块以及发送和接收逻辑模块的Verilog代码设计和其中关键问题的解决方法。之后设计了一种基于Wishbone总线的SPI协议IP软核。该IP软核通过参数化的方法实现设备数量为4、8、16时多设备间的通信,并自主决定设备的主从身份,通过设置对从机控制的优先级别仲裁多主设备对同一从机的控制权。同时能灵活设置通信模式和通信速率。分析以上设计目标并划分了功能子模块,说明了寄存器的设置过程,最后详细阐述了关键子模块的Verilog HDL实现过程,包括整体的设计思路和Wishbone总线接口模块、时钟逻辑模块以及内部控制寄存器模块的功能分析和Verilog代码设计。在完成设计的基础上,采用业界认可的仿真软件Modelsim和QuartusⅡ对设计的两种IP软核分别进行了RTL级功能和时序仿真验证,结果表明两种SPI协议IP软核设计正确,所有功能都达到预期的目标,仿真验证顺利通过。
[Abstract]:With the rapid development of integrated circuit technology, SOC technology has been paid more and more attention and application. Especially the emergence of on-chip bus technology and IP technology make them become the mainstream technology in IC design. However, the development of SOC is also facing great challenges, mainly IP multiplexing technology and IP interconnection technology. Therefore, the study of IP multiplexing technology is of great significance for the development of SOC. SPI is a synchronous, high-speed, full-duplex communication bus developed by Motorola Company, because of its few signal lines. The simple structure has been integrated into communication bus by more and more chips. Based on this, two reusable and configurable SPI protocol IP soft cores are designed to provide flexible SPI interface for IP interconnection in SOC design. This fully meets the development requirements and development direction of SOC technology. It is of great significance and practical value for the industry and the popularization and application of SPI. In this paper, two reusable SPI protocol IP soft cores are designed by using top-down design idea. Among them, SPI protocol IP soft core based on microcontroller is designed. The design focuses on the SPI host function, A design goal has been set so that it can communicate with eight slave computers, set the communication rate and select the transmission mode, and separate the receiving logic from the transmission logic. A double buffer mechanism is designed for sending and receiving data. According to the design objective, the sub-modules are divided and the complete block diagram of module interconnect is given. The register setting is explained, and the Verilog HDL implementation process of the key sub-modules is discussed. Including design thinking analysis, microcontroller interface module, The Verilog code design of the clock logic module and the sending and receiving logic module and the solution of the key problems are also presented. Then, a SPI protocol IP soft core based on Wishbone bus is designed. The IP soft core is realized by parameterization method. The number of equipment is 4 / 8, and the communication between more than 16:00 devices, And independently determine the master-slave status of the device, By setting the priority control of the slave to arbitrate the control over the same slave, the communication mode and the communication rate can be set flexibly. The above design objectives are analyzed and the functional sub-modules are divided, and the process of setting up the register is explained. Finally, the Verilog HDL implementation process of the key sub-modules is described in detail, including the whole design idea and the Wishbone bus interface module, the function analysis of the clock logic module and the internal control register module, and the Verilog code design. Two kinds of IP soft cores designed are verified by RTL level and time sequence simulation using Modelsim and Quartus 鈪，

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