基于最小门延时技术的高速时间测量电路研究

发布时间：2018-03-10 18:23

本文选题：时间数字转换器　切入点：游标延迟链　出处：《宁波大学》2017年硕士论文　论文类型：学位论文

【摘要】：在过去的几十年中,集成电路工艺技术得到很大发展,尺寸越来越低,集成度越来越高,功耗越来越小,对于集成电路设计做出很大贡献。时间数字转换器(TDC)也随着这次发展得到很大提升,TDC在集成度、芯片面积、工作速度、功耗和测量分辨率都有很大提高。TDC在航空航天、激光雷达和高能物理等方面有着重要的作用。因此,设计出高分辨率的TDC有着重要的现实意义。本文通过对不同TDC结构性能进行分析,最终采用游标延迟链型TDC结构,游标延迟链型TDC可以达到高分辨率和宽时间测量范围。同时对于TDC的开始和结束控制信号进行了分析,没有采用外部信号进行直接控制,因为外部信号上升沿时间比较长,影响了TDC中门翻转时间,从而增加了门延迟时间,降低了TDC的分辨率。分析了不同上升沿阶跃信号在门延迟中的延迟时间,上升沿时间越短对应的门延迟时间越短,通过内部设计的电压比较器输出信号作为TDC的控制信号。通过这种方式就可以提高传统游标延迟链型TDC分辨率。对TDC总体框架图和时序图进行了设计和分析,TDC电路主要包括电压比较器电路、振荡器电路、Arbiter电路和16进制计数器电路。电压比较器电路产生陡峭的阶跃信号控制TDC开始和结束信号;两路振荡器电路作为TDC游标延时链;Arbiter电路精确判断两路信号相位相差5ps判决跳变;16进制计数器电路扩展TDC时间测量范围。对于TDC电路中误差转移模型和反相器单元延时模型进行了分析。针对高速TDC电路输出可能出现误码或者丢码的现象,设计了输入端冗余消除电路、伪“01”消除电路和计数器防抖动电路。最后分析了TDC中误差影响,给出了直接校正和间接校正两种方法对TDC进行校准。最后,在TSMC 180nm工艺下完成TDC设计,利用Cadence Spectre工具对电路进行仿真分析,得到TDC的分辨率为5.3ps,功耗为6.5mW,版图面积为0.13mm2,动态范围为7.2ns。结果表明,TDC的性能良好,达到了预期设计目标。
[Abstract]:In the past few decades, the integrated circuit technology has been greatly developed, the size is getting lower and lower, the integration level is getting higher and higher, the power consumption is getting smaller and smaller. TDC has been greatly improved in integration, chip area, working speed, power consumption and measurement resolution with the development of TDC in aeronautics and astronautics. Lidar and high energy physics play an important role. Therefore, the design of high resolution TDC has important practical significance. By analyzing the performance of different TDC structures, the Vernier delay chain TDC structure is adopted in this paper. Vernier delay chain TDC can achieve high resolution and wide time measurement range. At the same time, the start and end control signals of TDC are analyzed. The gate flipping time in TDC is affected, thus the gate delay time is increased and the resolution of TDC is reduced. The delay time of different rising edge step signals in gate delay is analyzed. The shorter the rising edge time is, the shorter the gate delay time is. The output signal of the voltage comparator designed internally is used as the control signal of the TDC. In this way, the resolution of the traditional Vernier delay chain TDC can be improved. The overall frame diagram and sequence diagram of the TDC are designed and analyzed. The circuit mainly includes voltage comparator circuit, Oscillator circuit arbitrer circuit and hexadecimal counter circuit. Voltage comparator circuit generates steep step signal to control TDC start and end signal; The two-channel oscillator circuit is used as the TDC Vernier delay chain arbitrer circuit to accurately judge the phase difference between two signals by 5 PS decision jump / hexadecimal counter circuit to extend the range of TDC time measurement. For the error transfer model and inverter single in TDC circuit. The meta-delay model is analyzed. The error or loss of code may occur in the output of high-speed TDC circuit. The redundancy elimination circuit of input terminal, pseudo-" 01 "cancellation circuit and counter anti-jitter circuit are designed. Finally, the effect of error in TDC is analyzed, and two methods of direct correction and indirect correction to calibrate TDC are given. The design of TDC is completed under the TSMC 180nm process. The circuit is simulated and analyzed by Cadence Spectre tool. The result shows that the resolution of TDC is 5.3 pss, the power consumption is 6.5 MW, the layout area is 0.13 mm ~ 2, and the dynamic range is 7.2 ns.The results show that the performance of TDC is good and the expected design goal is achieved.
【学位授予单位】：宁波大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402

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