基于FPGA的高精度大动态延时系统设计与实现

发布时间：2018-03-18 10:39

本文选题：延时系统　切入点：锁相环　出处：《电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：高精度大动态延时系统在电子系统中有广泛的应用空间。延时电路的研究方法呈现多元化,主要分为光纤延时、模拟电路延时、数字电路延时。每一类延时方法都有各自的优缺点,很难同时满足高精度、大动态范围、集成化等性能指标。随着FPGA技术的发展,提供了在器件内部构建高精度大动态延时系统的条件。由于FPGA芯片的许多优良特性,广泛应用于雷达系统,延时系统与其他信号处理模块集成于芯片内部,将会有非常重要的工程意义。本文从实际工程应用出发,设计了一个对信号进行高精度大动态延时的系统。主要完成了以下工作。1.对延时电路的设计方案进行了归纳总结,得出高精度大动态延时电路的设计思路,分为粗细延时的策略。将FPGA相关的延时方案进行了深入的分析,总结了粗细延时在FPGA内部实现的各种设计方法。通过对比各种方案,确立了延时系统的设计方案。对延时系统方案中影响精度的关键因素进行了探讨。2.延时系统设计方案中,核心的技术是对锁相环进行高精度相位调整操作。详细分析了锁相环的原理与结构,并对器件内部嵌入的PLL结构进行了说明。对扫描链中参数之间的关系进行了梳理,重点介绍了锁相环的重配置和动态相位调整功能。3.结合工程指标,完成了高精度大动态延时系统的整体设计与实现,包括计数器延时模块、具有动态相位调整功能的锁相环模块,同频异相采样模块,线性调频信号产生模块,串口通信模块。对每一模块的设计原理和方法都做了说明。解决了异步时钟采样产生亚稳态的问题。4.基于FPGA开发板,将整个延时系统的每一个模块都做了细致的分析。利用仿真软件对延时系统的高精度实现做了精确的分析。通过改变延时量,进行多次测量,分析出延时系统的误差量,并总结出误差的来源。验证了设计的合理性与正确性。延时系统达到了性能指标。
[Abstract]:High precision and large dynamic delay system has wide application space in electronic system. The research methods of delay circuit are diversified, mainly divided into optical fiber delay, analog circuit delay, Digital circuit delay. Each type of delay methods have their own advantages and disadvantages, it is difficult to meet the high accuracy, large dynamic range, integration and other performance indicators. With the development of FPGA technology, The condition of constructing high precision and large dynamic delay system inside the device is provided. Because of many excellent characteristics of FPGA chip, it is widely used in radar system, and the delay system is integrated with other signal processing modules inside the chip. This paper designs a system of high precision and large dynamic delay for signal. 1. The design scheme of delay circuit is summarized. The design idea of high precision and large dynamic delay circuit is obtained, which is divided into thick and fine delay strategy. The delay schemes related to FPGA are analyzed deeply, and various design methods of realizing thick and fine delay in FPGA are summarized. The design scheme of the delay system is established. The key factors influencing the precision of the delay system scheme are discussed. 2. In the design scheme of the delay system, The key technology is to adjust the phase of PLL with high precision. The principle and structure of PLL are analyzed in detail, and the embedded PLL structure is explained. The reconfiguration of PLL and the function of dynamic phase adjustment. 3. Combined with engineering indexes, the overall design and implementation of high precision and large dynamic delay system are completed, including counter delay module. Phase-locked loop module with dynamic phase adjustment function, same frequency and different phase sampling module, linear frequency modulation signal generating module, Serial communication module. The design principle and method of each module are explained. The problem of asynchronous clock sampling to produce metastable state is solved. 4. Based on FPGA development board, Each module of the whole delay system is analyzed in detail. The high precision realization of the delay system is analyzed accurately by using the simulation software. The error of the delay system is analyzed by changing the delay quantity and measuring it many times. The source of the error is summarized. The rationality and correctness of the design are verified. The delay system achieves the performance index.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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