系统级异构多核混合精度可编程模拟器实现

发布时间：2018-03-19 22:21

本文选题：异构多核　切入点：模拟器　出处：《合肥工业大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着技术的进步,人们对处理器的运算能力的要求不断提高,人们对其要求也不断随之提高,异构多核片上系统(Multi-Processors System on Chip, MPSoC)应运而生。异构多核片上系统具有结构的复杂多变性,常规仿真工具和基于FPGA的硬件模拟器难以完全满足异构多核片上系统的设计、分析需求;此时,系统级的混合精度软件模拟器成为研究多核芯片架构、性能的重要工具之一。研究、设计异构多核片上系统模拟器成为一项重要的工作。当前,对传统的单核、多核CPU模拟器的研究已经广泛展开,并取得了许多成果,但对MPSoC的模拟器的研究工作,特别是针对面向高密度计算的MPSoC(MPSoC for High-Density Computing,HDCMPSoC)的模拟器研究工作进展有限。本文设计与实现了一种以HDCMPSoC为目标系统的系统级异构多核混合精度可编程模拟器。该模拟器具有超大规模、可配置系统结构的特性,可以提供包括运算数据、运行周期统计、多核并行度统计和网络占用率统计在内的仿真结果,同时支持混合精度运算单元的切换。本文的工作如下展开:首先,本文描述以C++实现目标HDCMPSoC模拟器的具体方法和过程,包括模拟器模块的实现与系统集成,以及非模块功能的实现;然后,本文通过实验,证实了模拟器的功能正确性和性能优越性。实验结果表明:模拟器支持最大64×128网络的系统规模,可以稳定运行具有一定复杂度的算法应用,且相比常规仿真软件有巨大的速度优势,其混合精度运算单元切换功能可有效提供速度与精度的灵活选择,模拟器满足设计要求。
[Abstract]:With the development of technology, people's demand for processor's computing power is increasing, and people's demand for processor's computing ability is also increasing. Multi-processors System on chip (MPSoC) emerged as the times require. The system on heterogeneous multi-core chip has complex variability of structure, so it is difficult for the conventional simulation tools and hardware simulator based on FPGA to fully meet the design of heterogeneous multi-core on-chip system. At this time, the system level hybrid precision software simulator has become one of the most important tools to study the architecture and performance of multi-core chips. The research of multi-core CPU simulator has been carried out extensively, and many achievements have been made, but the research work of MPSoC simulator, Especially, the research progress of MPSoC(MPSoC for High-Density computing simulator for high-density computing is limited. This paper designs and implements a system-level heterogeneous multi-core hybrid precision programmable simulator with HDCMPSoC as its target system. The characteristics of configurable system structure can provide simulation results including operation data, running cycle statistics, multi-core parallelism statistics and network occupancy statistics. The work of this paper is as follows: firstly, this paper describes the method and process of realizing the target HDCMPSoC simulator with C, including the realization of the simulator module and the integration of the system. And the realization of non-module function. Then, through the experiment, the correctness and performance superiority of the simulator are verified. The experimental results show that the simulator supports the maximum system size of 64 脳 128 network. The algorithm with certain complexity can run stably, and it has great speed advantage compared with the conventional simulation software. The switching function of its hybrid precision operation unit can effectively provide the flexible choice of speed and precision, and the simulator can meet the design requirements.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332;TN47

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