基于FPGA的图像处理加速器研究

发布时间：2018-03-20 09:21

本文选题：FPGA　切入点：图像处理加速器　出处：《武汉工程大学》2015年硕士论文　论文类型：学位论文

【摘要】：21世纪是电子信息时代,其中多媒体技术的快速发展使数字图像处理被广泛的应用到各行业中,如安防、气象、交通、航天航空、工业检测等。随着图像处理数据的不断增加,采用软件方案处理图像已经无法满足实时性的需求,而微电子技术正向高速、高效、高集成化、高可靠性发展,使基于硬件平台的数字图像处理系统更具优势。现场可编程门阵列(Field Programmable Gate Array,FPGA)就是一种比较理想的硬件解决方案,如今基于FPGA的图像处理加速器研究成为国内外的热门课题。本文以FPGA为平台,采用Verilog HDL硬件描述语言,研究一个可配置图像处理加速器,实现分辨率在1024*a(a为自然数)以内,256灰度级的任意图像大小的中值滤波和边缘检测处理。通过SPI总线协议,外部CPU可读写FPGA内自定义寄存器,设定图像大小及模式选择等参数,完成不同需求的中值滤波或边缘检测处理,同时将处理完的数据缓存到异步FIFO存储器中。在设计中,遵循速度与面积互换原则,挖掘算法并行性和流水结构,通过改进算法、时序约束等措施,提高顶层模块的处理速度,从而提高图像处理速度,达到加速的效果。图像处理加速器的设计是在Altera公司的Quartus II 14.0开发环境下进行的,仿真是在Mentor公司的Modelsim SE 10.2环境下进行的。综合仿真结果显示,本设计能够较好的完成设定的图像处理功能,最高频率可达128.8Mhz,图像数据处理流量高达1Gbps,对于800*600分辨率的8位灰度图像进行中值滤波和边缘检测处理,可达到每秒260帧。本文的研究对FPGA在图像处理硬件加速器中的应用做了探索性的尝试,提出了一种图像处理加速器研究思路与实现方法,设计了基于FPGA的数据处理流量高达1Gbps的图像处理加速器。对基于FPGA的图像处理加速器的研究有着积极的意义和参考价值。
[Abstract]:21th century is the era of electronic information. With the rapid development of multimedia technology, digital image processing has been widely used in various industries, such as security, meteorology, transportation, aerospace, industrial detection and so on. The application of software to image processing has not been able to meet the real-time requirements, while the microelectronics technology is developing at a high speed, high efficiency, high integration and high reliability. It makes the digital image processing system based on hardware platform more advantageous. Field Programmable Gate Array Field Programmable Gate FPGA is an ideal hardware solution. Nowadays, the research of image processing accelerator based on FPGA has become a hot topic at home and abroad. Based on FPGA and Verilog HDL hardware description language, a configurable image processing accelerator is studied in this paper. The median filtering and edge detection processing of arbitrary image size with a resolution of 1 024 ~ (a) is realized. Through the SPI bus protocol, the external CPU can read and write the custom registers in the FPGA, and set the parameters of image size and mode selection, etc. At the same time, the processed data is cached into the asynchronous FIFO memory. In the design, the parallelism of algorithm and income structure are mined according to the principle of speed and area exchange, and the algorithm is improved. In order to improve the processing speed of the top layer module and achieve the acceleration effect, the design of the image processing accelerator is carried out under the development environment of Quartus II 14.0 of Altera Company. The simulation is carried out under the environment of Modelsim SE 10.2 of Mentor Company. The comprehensive simulation results show that this design can accomplish the set image processing function well. The highest frequency can reach 128.8 MHz, and the flow of image data is up to 1 Gbps.The median filter and edge detection are used for 800 or 600 resolution 8-bit grayscale images. In this paper, the application of FPGA in image processing hardware accelerator is explored, and a research method of image processing accelerator is proposed. An image processing accelerator with data processing flow of up to 1Gbps based on FPGA is designed, which has positive significance and reference value for the research of image processing accelerator based on FPGA.
【学位授予单位】：武汉工程大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP391.41;TN791

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