面向存储系统的光片上网络设计

发布时间：2018-03-20 22:40

本文选题：片上网络　切入点：存储系统　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：多核芯片的出现和设计使得在2020年高性能计算实现E级浮点计算能力成为可能。随着处理器核数目的增加,对于高带宽,低延时存储访问网络设计的需求越来越明显。当处理器核与存储系统通信中数据传输速率提升时,电互连方式面临巨大的传输能耗和布线困难。此外,存储访问带宽在现有电互连方式下提升有限,多核芯片中处理器核对数据的存取将产生巨大的延时。因此,电互连结构下访问存储系统的能耗、互连面积、带宽和延时正在成为制约系统整体性能提升瓶颈,高性能计算系统面临“内存墙”问题。使用三维集成技术处理器核、存储系统和光片上网络将集成于同一芯片中。本文的研究重点在于利用多层硅沉积技术,设计一种面向存储系统的光片上网络,提高片上处理器核访问存储系统的并行性。首先,我们分析了IP核与存储系统之间通信流量的特性,针对该流量特性设计了一种适用于IP核与存储系统通信的可扩展拓扑结构。为实现对存储系统的并行访问,存储系统以最小并行访问单位“栈”(rank)进行划分。拓扑结构中使用一组环形波导连接所有IP核和栈。IP核与不同栈的通信通过不同环形波导进行区分,且在同一环形波导中来自不同IP核的存储访问请求通过不同波长进行区分。通过对网络中波长资源和微环的精确配置,实现了IP核与栈之间并行无阻塞通信。其次,我们对IP核与网络间通信接口、栈与网络间通信通信接口进行了研究。在栈的网络接口中配置缓存计数模块,用于监控存储访问请求处理情况。当缓存计数超过预定阈值时,栈接口将通过光片上网络向IP核进行广播,由此控制存储访问流量,避免存储访问请求丢失。IP核接口和栈接口中还配置了流水线模式的分布式存储访问控制器,用于实现并行化存储访问地址解析,缩短存储访问请求处理延时。最后,我们使用DRAMSim仿真器对所提出的光片上网络与传统电总线结构进行仿真对比。仿真中采用PARSEC测试标准中提取的存储访问流量。仿真结果表明使用所提出的光片上网络连接4栈存储系统时,平均存储访问带宽提升1.9倍,仿真时间内执行的存储访问请求数目平均增长1.95倍,平均存储访问延时下降53.2%;连接8栈存储系统时,平均存储访问带宽提升2.63倍,仿真时间内执行的存储访问请求数目平均增长2.52倍,平均存储访问延时下降89.8%。能耗分析结果表明本文所设计光网络中单位比特数据的传输能耗明显低于传统电总线互连方式能耗。在解决未来高性能计算中所面临的存储访问瓶颈问题时,本文的设计具有很好的应用前景。
[Abstract]:The emergence and design of multi-core chips make it possible to implement E-level floating-point computing in 2020 for high-performance computing. The demand of low-delay memory access network design is becoming more and more obvious. When the data transmission rate in the communication between processor core and storage system increases, the electrical interconnection mode faces enormous transmission energy consumption and wiring difficulties. The memory access bandwidth is limited under the existing electrical interconnection mode, and the access to the data checked by the processor in the multi-core chip will have a huge delay. Therefore, the energy consumption and the interconnection area of the access storage system under the electrical interconnection structure will be greatly delayed. Bandwidth and delay are becoming the bottleneck to improve the overall performance of the system. High-performance computing systems face the "memory wall" problem. Memory system and optical on-chip network will be integrated into the same chip. The emphasis of this paper is to design a storage system-oriented optical on-chip network using multilayer silicon deposition technology. To improve the parallelism of on-chip processor core access storage system. Firstly, we analyze the characteristics of communication traffic between IP core and storage system. An extensible topology for communication between IP core and storage system is designed to achieve parallel access to storage system. The storage system is divided by the minimum parallel access unit "stack" rank. In the topology, a set of ring waveguides are used to connect all IP cores and the communication between stack. IP cores and different stacks through different ring waveguides. The memory access requests from different IP cores in the same ring waveguide are distinguished by different wavelengths. By the accurate configuration of wavelength resources and microrings in the network, parallel non-blocking communication between IP cores and stacks is realized. We study the communication interface between IP core and network, the communication interface between stack and network. The cache counting module is configured in the network interface of stack to monitor the processing of storage access request. The stack interface will broadcast to the IP core through the optical on-chip network, thereby controlling the storage access flow and avoiding the loss of memory access request. The IP core interface and the stack interface are also equipped with a distributed storage access controller with pipeline mode. It is used to realize parallel storage access address resolution and shorten the delay of memory access request processing. Finally, We use the DRAMSim simulator to compare the proposed optical on-chip network with the traditional electric bus architecture. In the simulation, the memory access flow extracted from the PARSEC test standard is used. The simulation results show that the proposed optical chip is used to access the Internet. When connecting to the 4 stack storage system, The average storage access bandwidth increased 1.9 times, the number of memory access requests executed in the simulation time increased 1.95 times, the average storage access delay decreased 53.2 times, and the average storage access bandwidth increased 2.63 times when connected to the 8-stack storage system. The number of memory access requests executed during simulation time increased by an average of 2.52 times, The energy consumption analysis results show that the energy consumption of the unit bit data transmission in the optical network designed in this paper is obviously lower than that of the traditional electric bus interconnection mode. The results of energy consumption analysis show that the energy consumption of the unit bit data transmission in the optical network designed in this paper is obviously lower than that in the traditional electric bus interconnection mode. When storing access bottlenecks, the, The design of this paper has a good application prospect.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47;TP333

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