高速时间交织模数转换器数字校准技术研究

发布时间：2018-03-22 00:37

本文选题：时间交织模数转换器　切入点：通道失配　出处：《中国科学技术大学》2017年博士论文　论文类型：学位论文

【摘要】：模数转换器(Analog-to-Digital converter,ADC)作为连接模拟世界与数字世界的纽带,在现代通信、图像采集、医疗电子等众多领域中起到非常关键的作用。伴随着CMOS工艺的快速演进,器件最小尺寸按比例缩小,带来工作速度的提升和面积的减小,但电源电压的降低和晶体管本征增益的下降导致模拟电路的非理想型效应更加明显,模数转换器的速度与精度性能己趋于现有条件下的物理极限。时间交织ADC(Time-interleaved ADC,TIADC)以多片低速高精度ADC交替采样来实现高速采样,是一种有效的实现高速高精度的方式,目前超高速ADC几乎都采用这种架构。然而由于制造工艺上的偏差,时间交织ADC的通道间存在各种各样的失配效应严重地降低了其动态性能,这其中主要包括失调失配误差、增益失配误差和采样时间失配误差。利用模拟电路中对各子通道进行严格的匹配设计收到的效果甚微,而利用数字电路低功耗、高可靠、灵活度好等优势,通过数字校准来实现误差的消除已然成为当前高速TIADC设计的主流技术。本论文研究高速时间交织ADC的后台盲自适应全数字校准技术。首先通过对高速时间交织ADC进行系统级建模,从理论层面分析和验证了各种失配误差对时间交织ADC的影响;然后在调研和分析国内外校准技术的优缺点基础上,提出了两种校准数字校准技术,并从行为级对算法进行了验证;接着搭建相应的电路级验证平台,实验结果进一步证明了本校准算法的有效性和优越性,最后完成了部分校准算法的ASIC设计。具体研究工作如下:第一,提出了一种基于统计的自适应校准算法。基于统计的自适应数字校准算法其基本思想是利用各通道对同一输入信号进行采样,因此各通道输出信号的平均能量一致,能量的偏差则直接体现了系统的误差。对于失调失配误差和增益失配误差,提出基于自有通道的LMS迭代的自适应校准算法,并引入指数平均器提高收敛精度;对于采样时间失配误差,利用信号的平均能量特性以及信号的自相关特性来实现误差的估计,再利用改进Farrow结构分数延时滤波对误差进行校准。整个校准算法均在数字域实现,实现TIADC转换后信号的处理。校准算法结构简单,硬件实现比较容易,理论上对通道数没有严格的限制,可以扩展到任意通道数。第二,提出了一种基于信号调制的自适应校准算法。通过分析和确定误差频点的位置,利用信号调制来构建和杂散频点有着相同频谱的信号,基于相关运算实现误差估计,最后通过相减消除误差的影响,可同时实现增益失配误差和采样时间失配误差的校准。进一步提出利用指数平均器进行收敛曲线的平滑的方法,有效提高了校准精度和收敛速度。所提出的结构和校准技术对于奈奎斯特频带之内的输入信号(个别特殊频率点除外)均能有效校准。与已有算法相比,本校准算法在校准效果和硬件资源的开销上均有较大的优势。第三,基于SMIC 0.13μm工艺设计实现了一款12位、100MS/s流水线ADC,并将它作为子通道ADC搭建了四通道12位400MS/s时间交织ADC电路平台,该平台的输出作为激励信号输入到校准算法,完成了校准算法的FPGA验证。对于基于统计的全数字自适应校准方案,电路级验证结果表明,在三种失配误差大小分别为os=[0 0.05-0.05 0.1]、△g=[0 0.053-0.971 0.042]、△t=[0 1%2%-1%]Ts的条件下,输入信号为差分摆幅0.9Vpp(0.9FSR)频率为164.6 MHz的正弦信号,经过校准后时间交织ADC的SNDR和SFDR分别提高了48 dB和60.2 dB,分别达到71.2 dB和84.6 dB,有效位数ENOB为11.5 bits;对于基于信号调制的全数字自适应校准方案,在相同增益和采样时间失配误差条件下,电路级验证结果表明,校准前,SNDR和SFDR分别只有30.9 dB和33.8 dB,经过数字后台校准后,SNDR和SFDR分别提高了40.5 dB和54.7dB,达到71.4 dB和88.5 dB,校准后ADC的有效位数ENOB为11.52 bits。最后,基于SMIC 0.13μm工艺库,完成了基于LMS迭代的自有通道失调和增益失配联合校准算法的ASIC设计,后仿真结果表明所提出的数字校准技术能够有效抑制时间交织ADC通道失配误差所带来的杂散影响,提高TIADC的动态性能。
[Abstract]:Analog to digital converter (Analog-to-Digital converter ADC) as a connecting link between the analog world and digital image acquisition, in modern communication, and plays a very important role in many fields such as medical electronics. With the rapid development of CMOS technology, the smallest devices scaled down, and decrease the lifting speed of the area, decreased but the low supply voltage and transistor intrinsic gain leads to non ideal effect of analog circuit is more obvious, the speed and precision of ADC performance has become the physical limits under current conditions. The time interleaved ADC (Time-interleaved ADC TIADC) based on multi speed and high precision ADC alternate sampling to achieve high-speed sampling, is a the effective way to realize high speed and high precision, the ultra high speed ADC almost all adopt this framework. However, due to the deviation of the manufacturing process, time interleaved ADC channels Mismatch effect between the various severely reduced its dynamic performance, which mainly include offset mismatch error, gain mismatch error and sampling time mismatch error. By using the strict matching design received little effect on each sub channel analog circuit, digital circuit and low power consumption, high reliability, good flexibility and other advantages, is eliminated by digital calibration to achieve error has become the mainstream technology of high-speed TIADC design. Backgroundcalibration ADC full digital calibration technique is studied in this paper. Firstly, based on high speed time interleaved high speed time interleaved ADC system level modeling, and verified the mismatch error of interleaved ADC effect of time on theory; then based on the advantages and disadvantages of investigation and analysis of domestic and international calibration technology, puts forward two kinds of calibration of digital calibration technology, and from the behavior of the algorithm. Verified; then build the circuit level verification platform. The experimental results prove the validity and superiority of this calibration algorithm, finally completed the ASIC design of calibration algorithm. The main research work is as follows: first, we propose an adaptive calibration algorithm based on statistics. Based on the basic idea of the adaptive digital calibration algorithm statistical sampling is performed on the same input signal by the channel, so the average energy of each channel output signal, the deviation of energy directly reflects the system error. The offset mismatch error and gain mismatch error, an adaptive calibration algorithm based on iterative LMS private channel, and introduce and improve the accuracy of convergence average index; sampling time for mismatch error, error estimation is achieved using the autocorrelation characteristics of the average energy characteristic of signal and signal, the use of improved F The structure of arrow to calibrate the fractional delay filter error. The calibration algorithms are implemented in digital domain, realize TIADC conversion signal. The calibration algorithm has the advantages of simple structure, easy hardware implementation, the theory of the number of channels is not strictly limited, can be extended to any number of channels. Second, we propose an adaptive algorithm for signal calibration based on modulation. By analyzing and determining the error frequency position, using signal modulation to construct a frequency point and spurious signals with the same frequency spectrum, correlation operation to achieve error estimation based on the subtraction, eliminate the influence of error, calibration can be achieved simultaneously gain mismatch error and sampling time mismatch error. Further put forward the method of smooth convergence curve using exponential averager, effectively improve the calibration accuracy and convergence speed. The proposed structure and calibration techniques for Nyquist band The input signal within the (individual special frequency points except) are effective calibration. Compared with the existing algorithms, this algorithm has the advantages of large calibration in the calibration effect and the cost of hardware. Third, SMIC 0.13 m process design and implementation of a 12 bit pipelined ADC based on 100MS/s, and use it as a sub channel the ADC ADC circuit to build a platform four channel 12 bit 400MS/s time interleaved, the output of the platform as the excitation signal is input to the calibration algorithm, completed the FPGA verification calibration algorithm. The adaptive digital calibration scheme based on statistics, circuit level verification results show that the three kinds of mismatch error size respectively is os=[0 0.05-0.05 0.1]. G=[0 0.053-0.971 0.042], t=[0 1%2%-1%]Ts, the input signal is a differential amplitude 0.9Vpp (0.9FSR) frequency is 164.6 MHz sinusoidal signal, after calibration time interleaved ADC SNDR and SFDR respectively. The 48 dB and 60.2 dB, reached 71.2 dB and 84.6 dB respectively. The effective number of ENOB is 11.5 bits; for the full digital calibration scheme based on adaptive modulation signal, and at the same time sampling gain mismatch error conditions, circuit level verification results show that the calibration before SNDR and SFDR were only 30.9 and 33.8 dB dB, after the digital background calibration, SNDR and SFDR were increased by 40.5 dB and 54.7dB, reached 71.4 dB and 88.5 dB, after calibration the effective number of bits ENOB ADC for 11.52 bits. finally, SMIC 0.13 m process library based on complete ASIC design its own LMS channel iterative offset and gain mismatch calibration algorithm combined based on the results of simulation show that the spurious effects of digital calibration technique proposed can effectively inhibit the time interleaved ADC channel mismatching error and improve the dynamic performance of TIADC.

【学位授予单位】：中国科学技术大学
【学位级别】：博士
【学位授予年份】：2017
【分类号】：TN792

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