功控单轨电流模设计技术

发布时间：2018-03-22 23:20

本文选题：功控单轨电流模电路　切入点：功控休眠技术　出处：《宁波大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着集成电路芯片在电子产品上的运用越来越广泛,芯片的功耗问题也得到极大的关注,提高工作速度,减小芯片功耗也成了目前许多研究学者的重要目标。目前已有的减小功耗技术有许多,比如,双阈值技术,沟道长度偏置技术,输入矢量控制以及功控休眠技术。其中,功控休眠技术能够有效的减小空闲状态下的功耗,从而能达到减小总功耗的目的。因此,要想进一步实现高速、低功耗设计,将功控休眠技术运用到单轨电流模电路中,实现高速电路的同时降低空闲状态下的功耗是一项非常重要的目标。本学位论文研究了低功耗设计技术以及传统CMOS电路的功耗组成。将功控休眠技术很好的运用到单轨电流模逻辑电路中,并从电路建模分析、功控技术设计、近阈值电路设计等多方面对它进行功耗减小的研究。本文可分为以下几个部分:1、介绍低功耗设计技术的研究背景,分析功控单轨电流模设计技术研究的重要性。2、介绍电流模电路的工作原理以及双轨电流模电路的电路结构,并对单轨电流模电路设计需要注意的性能参数特点进行分析,这为后面将新的技术运用到单轨电流模上做准备。3、分析传统静态CMOS功控休眠技术的工作原理以及其性能参数,根据功控休眠技术的特点,将这种技术用于单轨电流模电路中,对功控单轨电流模电路进行建模分析,研究功控单轨电流模电路在工作状态和休眠状态时的功耗来源,以及分析功控休眠晶体管的尺寸的改变会产生的影响。设计新型的功控单轨电流模触发器,从结构上优化功控单轨电流模电路的功耗。将设计的功控单轨电流模电路与传统静态CMOS电路以及非功控的电流模电路进行对比,结果显示功控单轨电流模电路在漏功耗减小方面有显著的优势。4、结合功控单轨电流模电路的工作特性,采用近阈值设计技术进一步优化电路的性能。在近阈值条件下,分析了功控单轨电流模电路能正常工作的最小工作电压,并比较了功控单轨电流模电路、电流模电路以及传统静态CMOS电路在不同工作电压时候的性能参数。研究结果显示将近阈值设计技术运用到功控单轨电流模电路中能够有效的减小功耗和延时。
[Abstract]:With the application of IC chips in electronic products more and more widely, the problem of chip power consumption has been paid great attention to, and the speed of work has been improved. Reducing chip power consumption has also become an important goal of many researchers. There are many existing power reduction technologies, such as dual-threshold technology, channel length bias technology, input vector control and power control sleep technology. Power control sleep technology can effectively reduce the power consumption in idle state, so that the total power consumption can be reduced. Therefore, in order to further realize the design of high speed and low power consumption, power control sleep technology is applied to monorail current mode circuit. It is a very important goal to realize high speed circuits and reduce the power consumption in idle state. This dissertation studies the low power design technology and the power composition of traditional CMOS circuits. To a monorail current-mode logic circuit, And from the circuit modeling analysis, power control technology design, near threshold circuit design and other aspects of its power consumption reduction. This paper can be divided into the following parts: 1, introduce the research background of low-power design technology, This paper analyzes the importance of the research on power control monorail current mode design, introduces the working principle of the current mode circuit and the circuit structure of the dual track current mode circuit, and analyzes the characteristics of the performance parameters which should be paid attention to in the design of the monorail current mode circuit. This is the preparation for the application of the new technology to the monorail current mode. 3. The working principle and performance parameters of the traditional static CMOS power control dormancy technology are analyzed. According to the characteristics of the power control dormancy technology, this technology is used in the monorail current mode circuit. Modeling and analysis of power-controlled monorail current-mode circuit is carried out to study the power consumption source of power-controlled monorail current-mode circuit in working and dormant state. And analyze the influence of the size change of power control dormant transistor. Design a new type of power-controlled monorail current-mode flip-flop, The power consumption of power-controlled monorail current-mode circuit is optimized from structure. The power control monorail current-mode circuit is compared with traditional static CMOS circuit and non-power-controlled current-mode circuit. The results show that power control monorail current-mode circuit has significant advantages in reducing leakage power consumption. Combined with the working characteristics of power-controlled monorail current-mode circuit, the near-threshold design technique is used to further optimize the performance of the circuit. The minimum operating voltage of power control monorail current mode circuit is analyzed, and the power control monorail current mode circuit is compared. The performance parameters of the current mode circuit and the traditional static CMOS circuit under different operating voltages. The results show that the near-threshold design technology can effectively reduce power consumption and delay in power-controlled monorail current-mode circuits.
【学位授予单位】：宁波大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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