高速串行总线过孔结构优化及设计与仿真协同流程

发布时间：2018-03-24 00:37

本文选题：高速串行设计　切入点：过孔　出处：《电子技术应用》2017年08期

【摘要】：56 G PAM4已经是近年来高速串行总线设计的新热点,同时行业也开始关注56 G NRZ和112 G PAM4的实现。速率提升带来了通道设计的挑战,尤其是过孔结构的优化,是无源通道性能的关键指标。从两方面来介绍过孔结构优化,首先讨论如何确保优化的准确性,如何通过仿真测试校准的方法流程得到准确的过孔结构的S参数,准确的仿真是优化过孔结构的前提。在对测试结果校准的基础上讨论如何进行准确的过孔仿真,对比不同优化方式的结果及影响。同时,关注Cadence Sigrity新的HSSO(High Speed Structure Optimizer)工具及流程,提升了设计及仿真优化的效率,更重要的是提升了设计与仿真之间沟通的效率,并减少沟通不畅带来的质量问题。
[Abstract]:56G PAM4 has been a new hot spot in the design of high-speed serial bus in recent years. At the same time, the industry has begun to pay attention to the realization of 56G NRZ and 112G PAM4. This paper introduces the optimization of perforated structure from two aspects. Firstly, it discusses how to ensure the accuracy of the optimization, and how to obtain the accurate S parameters of the perforated structure through the flow of simulation test and calibration. Accurate simulation is the premise of optimizing the structure of perforation. On the basis of calibrating the test results, this paper discusses how to carry out accurate simulation of perforation, and compares the results and effects of different optimization methods. At the same time, it pays close attention to the new HSSO(High Speed Structure optimizer tool and flow chart of Cadence Sigrity. It improves the efficiency of design and simulation optimization and, more importantly, improves the efficiency of communication between design and simulation, and reduces the quality problems caused by poor communication.
【作者单位】：深圳市一博科技有限公司;Cadence深圳分公司;
【分类号】：TN41;TP391.9

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