FPGA核心电路CLB的设计与研究

发布时间：2018-03-24 02:05

本文选题：CLB　切入点：FPGA　出处：《西安电子科技大学》2015年硕士论文

【摘要】：FPGA (Field Programable Gate Array)即现场可编程门阵列,是在PAL(Programable Array Logic)、GAL(Gate Array Logic)、CPLD(Complex Programable Logic Device)等可编程器件的基础上进一步发展的产物。作为专用集成电路(ASIC)领域中的一种半定制电路,既解决了定制电路的不足,又克服了原有可编程器件门电路数有限的缺点。相比于国际FPGA公司多年的发展积累,国内FPGA技术的发展处于起步阶段,西安智多晶微电子抓住国产FPGA设计的迫切需求,依据客户定制的要求,设计了IST系列FPGA。论文基于IST项目中的FPGA可配置电路CLB(Configure Logic Block)的设计与优化,深入研究了FPGA器件逻辑配置模块的核心结构和原理,设计和优化CLB电路结构和性能,采用55nnm标准CMOS工艺,利用全定制设计方法设计电路,采用标准的全定制流程,利用VCS作为功能验证工具,利用Hspice做性能分析和优化,在工艺和工具上都有先进性,在设计原理上具有独创性。主要内容有如下：1.利用自上而下的设计方法,完成了CLB的核心单元PFU从顶层的结构设计到底层的模块实现。详细阐述了PFU的设计原理和思路,包括PFU的顶层设计以及模块划分,PFU核心模块Slice的顶层设计和Slice三大工作模式(Ripple mode, Logic mode, RAM mode)的功能定义,以及Slice在每种工作模式下的每个功能点的设计方案,完成了Slice功能要求的加法器、减法器、上行计数器、下行计数器,比较器、乘法器的设计,完成了规格要求的RAM模式电路的设计,实现了单双口RAM、信号连接和RAM的容量扩张。2.针对CLB的特点,搭建了具有高效率和符合CLB特点的验证平台,利用VCS工具,验证了CLB的各种模式以及其对应的功能的正确性。利用自动比对的标准位和波形的详细分析,完备而又直观的验证了CLB的功能,证明设计结果正确且符合要求。3.基于FPGA芯片对应的编程软件设计的要求和目标规格(Target spec)中的性能要求,对CLB的设计做了版图后仿真,在添加了寄生参数的前提下,分析各功能电路的负载并正确合理加入负载,同时利用Hspice的高精度器件时序模型,对目标规格要求的各功能的路径延时做了仿真,得到具体延时数据,并不断修改设计和器件尺寸,使仿真的延时达到规格要求,同时分析关键信号的波形,保证信号的完整性,达到了项目的性能指标要求。
[Abstract]:FPGA field Programable Gate array is the product of further development on the basis of PAL(Programable Array logic gate Array logic device and so on. As a semi-custom circuit in the field of ASICs, it solves the deficiency of custom circuit. Compared with the development and accumulation of international FPGA company for many years, the development of domestic FPGA technology is in its infancy, and Xi'an Zhi polycrystalline microelectronics seize the urgent need of domestic FPGA design. According to the requirements of customer customization, the IST series FPGA is designed. Based on the design and optimization of FPGA configurable circuit CLB(Configure Logic Block in the IST project, the core structure and principle of FPGA logic configuration module are deeply studied. To design and optimize the structure and performance of CLB circuit, adopt 55nnm standard CMOS process, design circuit with full custom design method, adopt standard full customization flow, use VCS as function verification tool, use Hspice to do performance analysis and optimization. Advanced in technology and tools, originality in design principle. The main contents are as follows: 1.Using top-down design method, In this paper, the core unit of CLB, PFU, is designed from the top structure to the bottom module. The design principle and thought of PFU are described in detail. Including the top-level design of PFU and the top-level design of Slice, the core module of Slice, and the definition of the functions of three working modes of Slice: Ripple mod, Logic mode, RAM mode, and the design scheme of each function point of Slice in each working mode. The design of the adder, subtracter, uplink counter, downlink counter, comparator and multiplier for Slice function requirement is completed. The design of RAM mode circuit with specifications is completed. The single and double port RAM, signal connection and capacity expansion of RAM are realized. According to the characteristics of CLB, a verification platform with high efficiency and accord with the characteristics of CLB is built, and the VCS tool is used. The correctness of various modes and corresponding functions of CLB is verified. The function of CLB is verified completely and intuitively by the detailed analysis of standard bits and waveforms of automatic alignment. It is proved that the design results are correct and accord with the requirements .3.Based on the requirements of programming software design corresponding to FPGA chip and the performance requirements in target specification, the post-layout simulation of the design of CLB is done, and the parasitic parameters are added to the design. The load of each functional circuit is analyzed and the load is added correctly and reasonably. At the same time, the path delay of each function required by the target specification is simulated by using the high-precision device timing model of Hspice, and the specific delay data are obtained. The design and the device size are modified constantly to make the simulation delay meet the specification requirements. At the same time, the waveform of the key signal is analyzed to ensure the integrity of the signal, and the performance requirements of the project are met.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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