一种高精度Sigma-Delta调制器的研究与设计

发布时间：2018-03-24 15:22

本文选题：开关电容　切入点：调制器　出处：《合肥工业大学》2015年硕士论文

【摘要】：高精度、低功耗模数转换器是当今的研究热点之一。在高精度模数转换方面,Sigma Delta模数转换器,在众多类型的ADC中脱颖而出,由于其采用过采样技术、噪声整形技术以及数字抽取滤波器,大大降低了对模拟电路设计的要求,同时实现了其它ADC无法达到的精度。但是也要看到,由于采用过采样技术,Sigma DeltaADC的所能达到的带宽有限,很难兼顾速度和精度。本文围绕Sigma Delta ADC中调制器部分(另一主要部分为数字抽取滤波器)开展研究与设计。首先采用Matlab Simulink工具进行了系统建模和仿真,充分考虑非理想因素对调制器系统性能的影响,包括运放的有限直流增益、有限带宽和压摆率、积分器输出摆幅、时钟抖动、采样电路热噪声等,对各非理想因素进行量化分析,为后续电路设计提供了设计依据。深入分析了非理想效应对调制器性能的影响。通过分析各结构的优缺点,结合项目设计指标,本文所设计Sigma Delta调制器最终采用三阶单环一位量化开关电容结构,结合系数优化,实现了高精度的设计要求。本文重点设计了第一级积分器,在调制器的第一级输入端加入了两个小电容,与采样电路构成一阶模拟低通滤波器,对进入调制器的信号带宽加以限制；在时序设计方面,采用了下极板采样技术,结合全差分电路的优势,大大减小了开关非理想效应对系统性能的影响；加入了斩波稳定电路,有效的降低了系统的噪声基底,抑制了低频噪声及系统失调,提高了调制器的动态范围。并详细讨论了电容最小值的取值,在减小开关电容采样电路热噪声的前提下,减小了芯片面积和功耗开支。采用Global Foundry 0.35um CMOS工艺,完成了本文提出的三阶单环一位量化调制器的电路设计。电源电压3.3V,过采样率为512,输入信号频率为73.8Hz,信噪比达到127dB,有效位数可以达到20bits,功耗为3.94mW,符合设计指标要求,满足高精度低功耗的应用需求。
[Abstract]:High precision, low power analog-to-digital converter is one of the hotspot of the research. In the aspect of high precision analog-to-digital conversion, Sigma Delta ADC, talent shows itself among all kinds of ADC, because it uses oversampling technology and noise shaping technique and a digital decimation filter, greatly reduces the analog circuit design requirements, while achieving the other ADC can not reach the accuracy. But it should be noted that due to the over sampling technique, Sigma DeltaADC can achieve the bandwidth is limited, it is difficult both speed and accuracy. This paper focuses on the Sigma Delta ADC modulator (the other part is the main part of the digital decimation filter) to carry out research and design. Firstly, the system modeling and simulation by Matlab Simulink, fully considering the influence of non ideal factors on the modulator performance of the system, including the finite DC gain of the amplifier, the limited bandwidth and slew rate, product Divider output swing, clock jitter, sampling circuit of thermal noise, quantitative analysis of the non ideal factors, provide a basis for the design of the circuit design. The in-depth analysis of the impact of non ideal effects on the modulator performance. Through analyzing the advantages and disadvantages of each structure, combined with the project design index, the design of Sigma Delta modulator the three order single loop single bit switched capacitor structure, with coefficient optimization, meet the design requirements of high precision. This paper focuses on the design of the first integrator, adding two small capacitance in the modulator first stage input, and the sampling circuit of first order analog low-pass filter, to limit the bandwidth of the signal into in the design of modulator; timing, the bottom plate sampling technique, combining the advantages of fully differential circuit, greatly reduce the switching of non ideal effects on the performance of the system influence; join The chopper circuit, effectively reduces the noise floor of the system, suppress the low-frequency noise and system imbalance, improve the dynamic range modulator. And the minimum value of capacitor is discussed in detail, in the premise of reducing the switching capacitor sampling circuit of thermal noise, reduce chip area and power consumption expenditure by Global Foundry 0.35um. CMOS process, completed the circuit design of the three order single loop single bit modulator. The power supply voltage 3.3V, the sampling rate is 512, the frequency of the input signal is 73.8Hz, the signal-to-noise ratio reached 127dB, the effective number of bits can reach 20bits, the power consumption is 3.94mW, meet the design requirements, meet the application requirements of high precision and low power consumption.

【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN761

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