新型Nanowire器件的测试、建模与仿真

发布时间：2018-03-25 07:32

本文选题：Nanowire器件　切入点：I-V特性　出处：《电子科技大学》2015年硕士论文

【摘要】：Nanowire器件的工艺尺寸进入纳米量级,其三维结构可以较好地节省面积,在较小的面积下实现所需的性能。在纳米级别的器件中,MOSFET器件应用较为广泛,本文利用的是台湾交通大学Nano Facility Center中心的Horng-Chih Lin教授及Kohui Lee博士制作版图,并在台湾交通大学流片的FET的Nanowire器件,器件类似于MOSFET的工作原理,即Nanowire FET的电流由栅压控制,通过对栅压的改变,达到控制器件开启及关闭的状态。器件沟道由掺杂的Si组成,并且器件为环栅结构。本文主要针对台湾交大的Nanowire器件进行测试、建模及仿真。其中,测试主要分为I-V特性测试及ESD测试。I-V特性测试结果表明,Nanowire器件的电气特性与普通MOS器件的电气特性类似,但是电流较小,在高温下可能会产生在加温后进入大电流稳态、性能衰减及特性紊乱三种失效。对于ESD测试,可以得到ESD的测试可得,三角形沟道形状较方形沟道形状来说,Vt2更大;相同沟道形状,沟道面积越大,Vt2越大。三角形沟道形状较方形沟道形状来说,It2更大;相同沟道形状,沟道面积越大,It2越大。建模主要利用加州大学伯克利分校BSIM研究小组提出的最新的适用于纳米级别器件的BSIM CMG模型。本文主要介绍了漏电流模型、本征电容模型和阈值电压模型,利用测试的Nanowire器件进行建模参数提取之后,利用Hspice进行仿真,主要测试Id-Vg与Id-Vd,将建模所得数据与测试所得数据相比较,可以看到,BSIM CMG模型适用于此Nanowire器件的建模,其误差在可以接受范围之内。本文主要利用Sentaurus仿真,通过所给的器件结构及漏极、栅极的掺杂浓度进行仿真。仿真为三维立体结构,其工艺参数、尺寸均按照工艺尺寸设定,仿真结果所得阈值电压、电气特性与测试结果基本一致,所得Id-Vg,其阈值电压与测试结果一致,且器件开启后按照指数变化,对于Id-Vd,其曲线在栅压变化时,漏电流增大,与测试结果一致。验证了仿真的可行性,可以为之后的Nanowire器件设计作为参考。
[Abstract]:The process size of Nanowire device is in nanometer order, its three-dimensional structure can save area better and realize the required performance in smaller area. It is widely used in nano-level devices. This paper uses Horng-Chih Lin Professor and Dr. Kohui Lee of Nano Facility Center Center of Taiwan Jiaotong University to make the layout, and Nanowire device of FET in Taiwan Jiaotong University flow sheet. The device is similar to the working principle of MOSFET, that is, the current of Nanowire FET is controlled by gate voltage. By changing the gate voltage, the device can be opened and closed. The device channel is made up of doped Si, and the device is a ring gate structure. In this paper, we test, model and simulate the Nanowire device of Taiwan Jiaotong University. The results of I-V characteristic test and ESD test .I-V characteristic test show that the electrical characteristics of MOS devices are similar to those of ordinary MOS devices, but the current is small, which may lead to high current steady-state at high temperature. For the ESD test, the ESD test is available, the triangular channel shape is larger than the square channel shape, the same channel shape, The larger the channel area, the larger the VT2. The triangular channel shape is larger than the square channel shape. The larger the channel area is, the larger the IT2 is. The modeling is mainly based on the latest BSIM CMG model for nanoscale devices proposed by the BSIM research team at the University of California, Berkeley. The leakage current model is mainly introduced in this paper. The intrinsic capacitance model and threshold voltage model are used to extract the modeling parameters from the tested Nanowire devices, and then the simulation is carried out by Hspice. The Id-Vg and Id-Vd are mainly tested, and the data obtained from the model are compared with the data obtained from the test. It can be seen that the BSIM CMG model is suitable for the modeling of this Nanowire device, and its error is within the acceptable range. In this paper, the device structure and drain, the doping concentration of the gate are simulated by Sentaurus simulation. The process parameters and dimensions are all set according to the process size. The simulation results show that the threshold voltage, the electrical characteristic and the test result are basically the same. The threshold voltage of the Id-Vg is the same as the test result, and the device changes exponentially after the device is opened. For Id-Vd, the leakage current increases when the gate voltage changes, which is consistent with the test results. The feasibility of the simulation is verified and can be used as a reference for the design of Nanowire devices.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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